XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 2

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

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Revision History
The following table shows the revision history for this document.
Virtex-4 FPGA User Guide
08/02/04
09/10/04
02/01/05
Date
Version
1.0
1.1
1.2
Initial Xilinx release. Printed Handbook version.
In
Removed Table 1-6: "BUFGMUX_VIRTEX4 Attributes". Updated
Table
Figure
these tables and figures were revised.
In
in
In Chapter 9, “System Monitor”:
Changed in Figure 9-4, Figure 9-5, Figure 9-7, Figure 9-8, Figure 9-9, Figure 9-10, Figure 9-21,
Figure 9-25, Figure 9-26, and Figure 9-27. Changes to the equation in the Temperature Sensor
section. The following tables had changes: Table 9-3, Table 9-5, Table 9-6, Table 9-9, Table 9-
11, Table 9-12, Table 9-14, and Table 9-15. Changes to the entire System Monitor Calibration,
System Monitor VHDL and Verilog Design Example sections.
In
“Clock Capable I/O”
In
In
Configuration Guide
Terminated Logic),” page
example:,” page
“Simultaneous Switching Output Limits,” page
Removed Chapter 9: System Monitor.
Table
Chapter 1, “Clock
Chapter 2, “Digital Clock Managers
Chapter 1, “Clock
Chapter 4, “Block RAM,”
Chapter 6, “SelectIO Resources,”
1-5, the new
1-9,
2-6.
Figure
302. Added rule “7” to
1-10,
Table
describes this information in detail. Edited
Resources”:
Resources”, revised
sections.
Figure
1-6. Revised
www.xilinx.com
281. Replaced LVDS_25_DCI with LVDCI_25 in
revised
1-13,
Figure
removed the device configuration section. The
“Reset,” page 151
Figure
“DCI in Virtex-4 FPGA Hardware,” page
(DCMs)”, changes to
Revision
“Global Clock
1-14, and
1-2,
R
306.
Figure
Figure
description and
1-5,
Buffers”,
1-16. Associated text around
Figure
“FACTORY_JF Attribute”
UG070 (v2.6) December 1, 2008
“SSTL (Stub-Series
Table
“Clock
1-6,
Figure
Table
1-1,
Regions”, and
“Compatible
Table
4-13.
1-7,
241. Added
1-2,
Virtex-4
and