XC5VFX30T-1FFG665C Xilinx Inc, XC5VFX30T-1FFG665C Datasheet - Page 82
![IC FPGA VIRTEX-5FX 30K 665-FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VFX30T-1FFG665C
Manufacturer Part Number
XC5VFX30T-1FFG665C
Description
IC FPGA VIRTEX-5FX 30K 665-FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Specifications of XC5VFX30T-1FFG665C
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
360
Clock Management
PLL
Core Supply Voltage Range
0.95V To 1.05V
Operating Frequency Max
600MHz
Operating
RoHS Compliant
Package
665FCBGA
Family Name
Virtex®-5
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2506752
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1583
XC5VFX30T-1FFG665C
XC5VFX30T-1FFG665C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VFX30T-1FFG665C
Manufacturer:
SUMIDA
Quantity:
30 000
Company:
Part Number:
XC5VFX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 97: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
T
T
PSDCMPLL_0
PHDCMPLL_0
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase
adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package
skew is not included in these measurements.
IFF = Input Flip-Flop.
Symbol
/
No Delay Global Clock and IFF
PLL in Source-Synchronous Mode
Description
(2)
with DCM and
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
Device
0.34
0.83
0.29
0.75
0.35
0.90
0.33
1.07
N/A
N/A
N/A
- 3
Speed Grade
0.40
0.89
0.38
1.12
0.36
0.87
0.32
0.78
0.35
0.92
0.37
1.11
0.29
1.42
- 2
0.40
0.94
0.39
1.17
0.37
0.92
0.32
0.83
0.35
0.96
0.41
1.16
0.33
1.46
- 1
Units
ns
ns
ns
ns
ns
ns
ns
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