XC5VFX30T-1FFG665C Xilinx Inc, XC5VFX30T-1FFG665C Datasheet - Page 14

• Manufacturer Part Number: XC5VFX30T-1FFG665C
• Description: IC FPGA VIRTEX-5FX 30K 665-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr

Specifications of XC5VFX30T-1FFG665C

• Number Of Logic Elements/cells: 32768
• Number Of Labs/clbs: 2560
• Total Ram Bits: 2506752
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Core Supply Voltage Range: 0.95V To 1.05V
• Operating Frequency Max: 600MHz
• Operating: RoHS Compliant
• Package: 665FCBGA
• Family Name: Virtex®-5
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 2506752
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1583; XC5VFX30T-1FFG665C

Table 27: GTP_DUAL Tile Quiescent Supply Current
GTP_DUAL Tile DC Input and Output Levels
Table 28
ended output voltage swing.
Consult UG196:Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further details.
Table 28: GTP_DUAL Tile DC Specifications
X-Ref Target - Figure 1
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
Notes:
1.
2.
3.
4.
I
I
I
AVCCPLLQ
Symbol
AVTTRXQ
AVTTTXQ
DV
I
Symbol
The output swing and preemphasis levels are programmable using the attributes discussed in UG196:Virtex-5 FPGA RocketIO GTP
Transceiver User Guide and can result in values lower than reported in this table.
Values outside of this range can be used as appropriate to conform to specific protocols and standards.
Typical values are specified at nominal voltage, 25°C.
Device powered and unconfigured.
Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
GTP_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTP_DUAL tiles in the target LXT or SXT device.
V
T
V
AVCCQ
DV
+V
V
R
OSKEW
CMOUT
C
SEOUT
R
V
CMIN
PPOUT
0
OUT
EXT
PPIN
IN
IN
summarizes the DC output specifications of the GTP_DUAL tiles in Virtex-5 FPGAs.
P
N
Quiescent MGTAVTTTX (transmitter termination) supply current
Quiescent MGTAVCCPLL (PLL) supply current
Quiescent MGTAVTTRX (receiver termination) supply current. Includes
MGTAVTTRXCQ.
Quiescent MGTAVCC (analog) supply current
Differential peak-to-peak input
voltage
Absolute input voltage
Common mode input voltage
Differential peak-to-peak output
voltage
Single-ended output voltage
swing
Common mode output voltage
Differential input resistance
Differential output resistance
Transmitter output skew
Recommended external AC coupling capacitor
(1)
(1)
DC Parameter
Figure 2
Figure 1: Single-Ended Output Voltage Swing
shows the peak-to-peak differential output voltage.
External AC coupled ≤ 3.2 Gb/s
External AC coupled > 3.2 Gb/s
DC coupled
DC coupled
MGTAVTTRX = 1.2V
TXBUFDIFFCTRL = 000,
TX_DIFF_BOOST = ON
TXBUFDIFFCTRL = 000,
TX_DIFF_BOOST = ON
Equation based
MGTAVTTTX = 1.2V
Description
www.xilinx.com
Conditions
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(2)
–400
Min
150
180
90
90
75
1200 – Amplitude/2
Typ
800
100
100
100
Figure 1
Typ
8.5
0.1
2.5
8
(1)
MGTAVTTRX
shows the single-
up to 1320
+ 400
2000
2000
1400
Max
Max
700
120
120
200
0.8
18
18
11
15
ds202_01_051607
V
SEOUT
Units
mA
Units
mA
mA
mA
mV
mV
mV
mV
mV
mV
mV
nF
ps
Ω
Ω
14