XC5VFX30T-1FFG665C Xilinx Inc, XC5VFX30T-1FFG665C Datasheet - Page 18

• Manufacturer Part Number: XC5VFX30T-1FFG665C
• Description: IC FPGA VIRTEX-5FX 30K 665-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr

Specifications of XC5VFX30T-1FFG665C

• Number Of Logic Elements/cells: 32768
• Number Of Labs/clbs: 2560
• Total Ram Bits: 2506752
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Core Supply Voltage Range: 0.95V To 1.05V
• Operating Frequency Max: 600MHz
• Operating: RoHS Compliant
• Package: 665FCBGA
• Family Name: Virtex®-5
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 2506752
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1583; XC5VFX30T-1FFG665C

Table 35: GTP_DUAL Tile Receiver Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
SJ Jitter Tolerance
SJ Jitter Tolerance with Stressed Eye
Using PLL_RXDIVSEL_OUT = 1 only.
Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
CDR 1st-order step size set to 2.
All jitter values are based on a Bit Error Ratio of 1e
Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.
R
JT_TJSE
JT_SJSE
R
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
Symbol
XOOBVDPP
F
XPPMTOL
R
R
GTPRX
XSST
XRL
3.75
2.50
2.00
1.00
500
500
100
3.2
3.2
3.2
(4)
Serial data rate
OOB detect threshold
peak-to-peak
Receiver spread-spectrum
tracking
Run length (CID)
Data/REFCLK PPM offset
tolerance
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Total Jitter with Stressed
Eye
Sinusoidal Jitter with
Stressed Eye
(6)
(1)
(2)
(6)
(4)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
–12
Description
.
RX oversampler not enabled
RX oversampler enabled
OOBDETECT_THRESHOLD = 100
Modulated @ 33 KHz
Internal AC capacitor bypassed
CDR 2
PLL_RXDIVSEL_OUT = 1
CDR 2
PLL_RXDIVSEL_OUT = 2
CDR 2
PLL_RXDIVSEL_OUT = 4
CDR 2
3.75 Gb/s
3.20 Gb/s
2.50 Gb/s
2.00 Gb/s
1.00 Gb/s
500 Mb/s
500 Mb/s OS
100 Mb/s OS
3.20 Gb/s
3.20 Gb/s
www.xilinx.com
nd
nd
nd
nd
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
-order loop disabled with
-order loop disabled with
-order loop disabled with
-order loop enabled
(3)
(3)
(3)
–5000
–1000
–200
–200
–100
0.30
0.40
0.40
0.40
0.30
0.30
0.30
0.30
0.87
0.30
Min
0.5
0.1
60
Typ
105
F
GTPMAX
1000
Max
165
150
200
200
100
0.5
0
Units
Gb/s
Gb/s
ppm
ppm
ppm
ppm
ppm
mV
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
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