XC4VFX12-11SFG363C Xilinx Inc, XC4VFX12-11SFG363C Datasheet - Page 342

• Manufacturer Part Number: XC4VFX12-11SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
342
IDELAYCTRL Timing
REFCLK - Reference Clock
The reference clock (REFCLK) provides a time reference to IDELAYCTRL to calibrate all
IDELAY modules in the same region. This clock must be driven by a global clock buffer
(BUFGCTRL). REFCLK must be F
MHz (IDELAYCTRL_REF_PRECISION) to guarantee a specified IDELAY resolution
(T
from the DCM, and must be routed on a global clock buffer. All valid M & D configurations
are supported. Use the DCM Wizard to determine the correct settings in order to create the
200 MHz reference clock.
RDY - Ready
The ready (RDY) signal indicates when the IDELAY modules in the specific region are
calibrated. The RDY signal is deasserted if REFCLK is held High or Low for one clock
period or more. If RDY is deasserted Low, the IDELAYCTRL module must be reset. The
implementation tools allow RDY to be unconnected/ignored.
timing relationship between RDY and RST.
Table 7-10
Table 7-10: IDELAYCTRL Switching Characteristics
RST Event 1
•
RST Event 2
•
•
F
IDELAYCTRL_REF_PRECISION
T
T
IDELAYRESOLUTION
IDELAYCTRL_REF
IDELAYCTRL_RPW
IDELAYCTRLCO_RDY
At RST Event 1, the RST pin is asserted.
At RST Event 2, the RST pin is deasserted.
At T
REFCLK
IDELAYCTRLCO_RDY
shows the IDELAYCTRL switching characteristics.
RST
RDY
Figure 7-14: Timing Relationship Between RST and RDY
Symbol
). REFCLK can be supplied directly from a user-supplied source or
1
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T
, after RST Event 2, RDY is asserted High.
IDELAYCTRL_RPW
IDELAYCTRL_REF
REFCLK frequency
REFCLK precision
Reset pulse width
Reset/Startup to Ready for IDELAYCTRL
2
± the specified frequency variation in
T
Description
IDELAYCTRLCO_RDY
UG070 (v2.6) December 1, 2008
Figure 7-14
Virtex-4 FPGA User Guide
UG070_7_14_032808
illustrates the
R