XC4VFX12-11SFG363C Xilinx Inc, XC4VFX12-11SFG363C Datasheet - Page 120

• Manufacturer Part Number: XC4VFX12-11SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
Additional Block RAM Features in Virtex-4 Devices
120
Optional Output Registers
Synchronous Clocking
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•
The clock-to-clock setup timing parameter is specified together with other block RAM
switching characteristics in the
Synchronous clocking is the special case, where the active edges of both port clocks occur
simultaneously:
•
•
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The optional output registers improve design performance by eliminating routing delay to
the CLB flip-flops for pipelined operation. These output registers have programmable
clock inversion as in CLB flip-flops. An independent clock enable input is provided for
these output registers. As a result the output data registers hold the value independent of
the input register operation.
There are no timing constraints when both ports perform a read operation.
When one port performs a write operation, the other port must not read- or write-
access the same memory location by using a clock edge that falls within the specified
forbidden clock-to-clock setup time window. If this restriction is ignored, a read
operation could read unreliable data, perhaps a mixture of old and new data in this
location; a write operation could result in wrong data stored in this location. There is,
however, no risk of physical damage to the device. If a read and write operation is
performed, the write will store valid data at the write location.
There are no timing constraints when both ports perform a read operation.
When one port performs a write operation, the other port must not write into the
same location, unless both ports write identical data.
When one port performs a write operation, the write operation succeeds; the other
port can reliably read data from the same location if the write port is in READ_FIRST
mode. DATA_OUT will then reflect the previously stored data.
If the write port is in either WRITE_FIRST or in NO_CHANGE mode, then the DATA-
OUT on the read port would become invalid (unreliable). Obviously, the mode setting
of the read-port does not affect this operation.
www.xilinx.com
Figure 4-5
Virtex-4 Data
shows the optional output register.
Sheet.
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R