XC4VFX12-11SFG363C Xilinx Inc, XC4VFX12-11SFG363C Datasheet - Page 210

• Manufacturer Part Number: XC4VFX12-11SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-11SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
210
Clock Event 1: Write Operation
During a Write operation, the contents of the memory at the address on the ADDR inputs
are changed. The data written to this memory location is reflected on the X/Y outputs
synchronously.
•
•
•
This is also applicable to the XMUX, YMUX, XB, YB, C
T
Clock Event 2: Read Operation
All Read operations are asynchronous in distributed RAM. As long as WE is Low, the
address bus can be asserted at any time. The contents of the RAM on the address bus are
reflected on the X/Y outputs after a delay of length T
LUT). The address (F) is asserted after clock event 2, and the contents of the RAM at
address (F) are reflected on the output after a delay of length T
WOSX
At time T
enabling the RAM for the following Write operation.
At time T
the RAM.
At time T
of the RAM and is reflected on the X/XMUX output at time T
event 1.
, T
WOSXB
AS
DS
WS
, T
before clock event 1, the address (2) becomes valid at the F/G inputs of
or T
before clock event 1, the write-enable signal (WE) becomes valid-High,
WOSYB
CYCK
, and T
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before clock event 1, the DATA becomes valid (1) at the DI input
SHCKOF5
after clock event 1.
OUT
ILO
(propagation delay through a
, and F5 outputs at time T
UG070 (v2.6) December 1, 2008
ILO
Virtex-4 FPGA User Guide
SHCKO
.
after clock
WOSCO
,
R