XC3S1200E-5FTG256C Xilinx Inc, XC3S1200E-5FTG256C Datasheet - Page 45
![IC FPGA SPARTAN3E 1200K 256FTBGA](/photos/6/71/67101/pk053-256_sml.jpg)
XC3S1200E-5FTG256C
Manufacturer Part Number
XC3S1200E-5FTG256C
Description
IC FPGA SPARTAN3E 1200K 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-5FTG256C
Number Of Logic Elements/cells
19512
Number Of Labs/clbs
2168
Total Ram Bits
516096
Number Of I /o
190
Number Of Gates
1200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Quantity:
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Manufacturer:
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Part Number:
XC3S1200E-5FTG256C(XC3S1200E-4FTG256I)
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DS312-2 (v3.8) August 26, 2009
Product Specification
BCIN[17:0]
A[17:0]
B[17:0]
RSTB
RSTP
RSTA
CEA
CEB
CEP
CLK
Figure 37: MULT18X18SIO Primitive
R
MULT18X18SIO
B[17:0]
RSTB
RSTB
CEB
CEB
CLK
CLK
BCIN[17:0]
Figure 38: Four Configurations of the B Input
CE
D
CE
D
BREG
BREG
BCOUT[17:0]
RST
RST
BCOUT[17:0]
P[35:0]
BCOUT[17:0]
DS312-2_28_021205
Q
Q
BREG = 1
B_INPUT = CASCADE
BREG = 1
B_INPUT = DIRECT
www.xilinx.com
X
X
Cascading Multipliers
The MULT18X18SIO primitive has two additional ports
called BCIN and BCOUT to cascade or share the multi-
plier’s ‘B’ input among several multiplier bocks. The 18-bit
BCIN “cascade” input port offers an alternate input source
from the more typical ‘B’ input. The B_INPUT attribute spec-
ifies whether the specific implementation uses the BCIN or
‘B’ input path. Setting B_INPUT to DIRECT chooses the ‘B’
input. Setting B_INPUT to CASCADE selects the alternate
BCIN input. The BREG register then optionally holds the
selected input value, if required.
BCOUT is an 18-bit output port that always reflects the
value that is applied to the multiplier’s second input, which is
either the ‘B’ input, the cascaded value from the BCIN input,
or the output of the BREG if it is inserted.
Figure 38
different settings for the B_INPUT attribute and the BREG
attribute.
B[17:0]
BCOUT[17:0]
BCOUT[17:0]
BCIN[17:0]
illustrates the four possible configurations using
BREG = 0
B_INPUT = CASCADE
BREG = 0
B_INPUT = DIRECT
DS312-2_29_021505
X
X
Functional Description
45
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