XC3S1200E-5FTG256C Xilinx Inc, XC3S1200E-5FTG256C Datasheet - Page 38
![IC FPGA SPARTAN3E 1200K 256FTBGA](/photos/6/71/67101/pk053-256_sml.jpg)
XC3S1200E-5FTG256C
Manufacturer Part Number
XC3S1200E-5FTG256C
Description
IC FPGA SPARTAN3E 1200K 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-5FTG256C
Number Of Logic Elements/cells
19512
Number Of Labs/clbs
2168
Total Ram Bits
516096
Number Of I /o
190
Number Of Gates
1200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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XC3S1200E-5FTG256C(XC3S1200E-4FTG256I)
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Functional Description
Block RAM Port Signal Definitions
Representations
RAMB16_S[w
RAMB16_S[w] with their associated signals are shown in
Figure 32a
defined in
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
38
Notes:
1.
2.
3.
4.
DIA[w
DIB[w
ADDRA[r
ADDRB[r
DIPB[p
DIPA[p
w
p
r
The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
A
Table
A
A
and
and r
A
B
and p
and w
–p
–p
A
]_S[w
SSRA
A
A
A
SSRB
B
B
B
CLKA
CLKB
B
Figure
WEA
WEB
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
23. The control signals (WE, EN, CLK, and
ENA
ENB
B
B
are integers representing the address bus width at ports A and B, respectively.
are integers that indicate the number of data path lines serving as parity bits.
are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
B
of
]
32b, respectively. These signals are
and
RAMB16_S
(a) Dual-Port
the
the
dual-port
W A
single-port
_S
W B
Figure 32: Block RAM Primitives
DOPA[p
DOA[w
DOPB[p
DOB[w
primitive
primitive
A
B
A
–p
B
–p
www.xilinx.com
–1:0]
–1:0]
A
B
–1:0]
–1:0]
Design Note
Whenever a block RAM port is enabled (ENA or
ENB = High), all address transitions must meet the data
sheet setup and hold times with respect to the port clock
(CLKA or CLKB), as shown in
requirement must be met even if the RAM read output is of
no interest.
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
SSR
CLK
WE
EN
(b) Single-Port
RAMB16_Sw
DS312-2 (v3.8) August 26, 2009
Table 103, page
Product Specification
DOP[p–1:0]
DO[w–p–1:0]
DS312-2_03_111105
142.This
R
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