XC3S500E-5FTG256C Xilinx Inc, XC3S500E-5FTG256C Datasheet - Page 49

• Manufacturer Part Number: XC3S500E-5FTG256C
• Description: IC FPGA SPARTAN-3E 500K 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-5FTG256C

• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 28: DLL Signals
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to elimi-
nate clock skew. The main signal path of the DLL consists of
an input stage, followed by a series of discrete delay ele-
ments or steps, which in turn leads to an output stage. This
path together with logic for phase detection and control
forms a system complete with feedback as shown in
Figure
using a counter-based delay line.
The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
DS312-2 (v3.8) August 26, 2009
Product Specification
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Signal
41. In Spartan-3E FPGAs, the DLL is implemented
R
Direction
Output
Output
Output
Output
Output
Output
Output
Input
Input
CLKFB
CLKIN
RST
Receives the incoming clock signal. See
external inputs to a DCM.
Accepts either CLK0 or CLK2X as the feedback signal. (Set the CLK_FEEDBACK
attribute accordingly).
Generates a clock signal with the same frequency and phase as CLKIN.
Generates a clock signal with the same frequency as CLKIN, phase-shifted by 90°.
Generates a clock signal with the same frequency as CLKIN, phase-shifted by 180°.
Generates a clock signal with the same frequency as CLKIN, phase-shifted by 270°.
Generates a clock signal with the same phase as CLKIN, and twice the frequency.
Generates a clock signal with twice the frequency of CLKIN, and phase-shifted 180°
with respect to CLK2X.
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency
clock signal that is phase-aligned to CLKIN.
Figure 41: Simplified Functional Diagram of DLL
Delay
1
Delay
2
Detection
Control
Phase
www.xilinx.com
Delay
n-1
described in
neously. Signals that initialize and report the state of the
DLL are discussed in
The clock signal supplied to the CLKIN input serves as a
reference waveform. The DLL seeks to align the rising-edge
of feedback signal at the CLKFB input with the rising-edge
of CLKIN input. When eliminating clock skew, the common
approach to using the DLL is as follows: The CLK0 signal is
passed through the clock distribution network that feeds all
the registers it synchronizes. These registers are either
internal or external to the FPGA. After passing through the
Delay
n
Description
Table
Table
30,
28. The clock outputs drive simulta-
Status
Table
DS099-2_08_041103
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
LOCKED
31, and
Logic.
Functional Description
Table 32
for optimal
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