EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 1004
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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1–46
Table 1–13. MegaWizard Plug-In Manager Options (Rate Match/Byte Order Screen) (Part 3 of 3)
Figure 1–15. MegaWizard Plug-In Manager—ALTGX (Protocol Settings Screen—GIGE and XAUI)
Stratix IV Device Handbook Volume 3
What is the byte ordering pad
pattern?
Note to
(1) If you want the rate matcher to insert or delete both the positive and negative disparities of the 20-bit rate matching pattern, enter the positive
disparity as pattern1 and negative disparity as pattern2.
Table
Protocol Settings Screen for GIGE and XAUI
ALTGX Setting
1–13:
Figure 1–15
MegaWizard Plug-In Manager.
shows the Protocol Settings screen for the GIGE and XAUI modes of the
When the byte ordering block does not find the byte
ordering pattern in the LSByte position of the data
coming out of the byte deseriazlier, it inserts this byte
ordering pad pattern such that the byte ordering
pattern is seen in the LSByte position of the receiver
parallel data on the rx_dataout port. Inserting this
pad character enables the byte ordering block to
restore the correct byte order.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“Byte Ordering Block”
section in the
Architecture In Stratix IV
Devices
February 2011 Altera Corporation
chapter.
Reference
Transceiver
Protocol Settings
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