EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 29

• Manufacturer Part Number: EP4SGX290KF40C3N
• Description: IC STRATIX IV GX 290K 1517FBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17248
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2624

Document Revision History
Table 9. Document Revision History (Part 2 of 3)
March 2011 Altera Corporation
September 2010
May 2010
April 2010
January 2010
November 2009
August 2009
June 2009
Date
Version
5.0
5.4
5.3
5.2
5.1
4.0
3.1
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Added the “I/O Jitter” section.
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Added:
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Updated the following with link to software patch:
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Updated with fix in “Automatic Clock Switchover”.
Added:
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Added the “Quartus II Mapping Issue with PCIe Interfaces Using the Hard IP Block”
section.
Added links to Table 3.
Added three headings with links to improve bookmark navigation.
Added “Fast Passive Parallel Mode Configuration Failures at High DCLK Frequency”
Added “FPP Mode Configuration Failures When the Minimum Hold Time (tDH) is set to 0
ns or 24 ns”
Updated “DPA Misalignment” and removed this issue from Production devices section
Updated Table 2
Updated “Higher Power Supply Current During Power-Up for VCCPD and VCCA_L/R”
Added “Transmitter PLL Lock (pll_locked) Status Signal”
Updated:
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Added “DPA Misalignment” section to production devices.
“Stratix IV GX Production Devices”
“M144K RAM Block Lock-Up”
“×8 and ×N Clock Line Timing Issue for Transceivers”
“Stratix IV GX Power-up Issue on Production Devices”
“M144K Write with Dual-Port Dual-Clock Modes”
“CRC Error Detection Feature”
“Remote System Upgrade”
“XAUI Functional Mode Failure”
“Timing Issue with Two Channels in Basic (PMA Direct) Configuration”
Added “M9K/M144K RAM Block Lock-up”
Renamed the “MLAB Issue with CRC Error Detection Feature” section to “CRC Error
Detection Feature” to more accurately reflect that this is a problem with the CRC circuit
within the MLAB. Revised the first sentence of this section.
Updated “×8 and ×N Clock Line Timing Issue for Transceivers”, “M144K Write with
Dual-Port Dual-Clock Modes”, and “CRC Error Detection Feature” sections
“Stratix IV GX Power-up Sequencing on Production Devices”
“×8 and ×N Clock Line Timing Issue for Transceivers”
Changes
Errata Sheet for Stratix IV GX Devices
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