EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 15

• Manufacturer Part Number: EP4SGX290KF40C3N
• Description: IC STRATIX IV GX 290K 1517FBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17248
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2624

Production Devices for Stratix IV GX Devices
Figure 9. Setting Voltage Levels
March 2011 Altera Corporation
■
Category 3: The configured ×N line data rate is greater than the maximum data
rate supported by the 1.2-V power supply level specified in
The Quartus II Compiler flags the following compilation error:
"Error: Transceiver channels clocked by clock divider atom
"top_alt4gxb:top_alt4gxb_component|central_clk_div0" are configured at a data
rate that is higher than that supported in Stratix IV GX/GT devices. The data rate
limitation is due to a ×N clock line issue. For more details on the impact of ×N
clock line issue, refer to the Stratix IV GX or Stratix IV GT Errata sheet section "×8
and ×N Clock Line Timing Issue for Transceivers."
Action: In the Quartus II software, on the Assignments menu, click Settings. Click
the “+” icon to expand Operating Settings and Conditions and select Voltage. Set
the VCCT_L/R, VCCL_GXBL/R, and VCCR_L/R voltage settings from 1.1V to
1.2V, as shown in
The Quartus II Compiler flags the following compilation error:
"Error: Transceiver channels clocked by clock divider atom
"top_alt4gxb:top_alt4gxb_component|central_clk_div0" are configured at a data
rate that is higher than that supported in Stratix IV GX/GT devices. The data rate
limitation is due to a ×N clock line issue. For more information about the impact of
×N clock line issue, refer to the Stratix IV GX or Stratix IV GT Errata sheet section
"×8 and ×N Clock Line Timing Issue for Transceivers."
Figure
9. Then recompile the project.
Errata Sheet for Stratix IV GX Devices
Table
2.
Page 15