EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 22

• Manufacturer Part Number: EP4SGX290KF40C3N
• Description: IC STRATIX IV GX 290K 1517FBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17248
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2624

Page 22
Errata Sheet for Stratix IV GX Devices
M144K Write with Dual-Port Dual-Clock Modes
Automatic Clock Switchover
CRC Error Detection Feature
f
1
1
There is no planned fix for the higher power-up current requirements.
M144K RAM blocks in dual-port dual-clock modes may fail to operate correctly,
affecting applications such as DCFIFO memories, where data is transferred between
two separate clock domains.
If you use Stratix IV GX ES devices with the Quartus II software version 9.0, you must
recompile your design and manually avoid all use of M144K RAM blocks in dual-port
dual-clock modes. The Quartus II software version 9.0 SP1 will automatically disable
use of dual-port dual-clock modes in all M144K RAM blocks. In both cases, your
design’s usage of M9K RAM blocks may increase as a result.
This issue is fixed in production devices.
You can download a software patch to help with M144K RAM blocks in dual-port
dual-clock mode failure at:
http://www.altera.com/support/kdb/solutions/rd04092009_699.html
The Automatic Clock Switchover feature may fail to operate correctly on
Stratix IV GX ES devices when the two clocks are running different frequencies. If
both clocks are running at the same frequency, there is no impact to your design. The
following modes are affected:
■
■
You may observe two possible issues:
■
■
Manual clock switchover mode operates correctly as expected and is not affected.
This issue is fixed in production devices.
The CRC Error Detection feature, when enabled, may cause the MLAB RAM blocks to
operate incorrectly in Stratix IV GX ES devices. Write operations in MLAB RAM
blocks are affected with all CRC Error Detection divisor settings.
The CRC Error Detection feature operates correctly as expected. FPGA configuration
bits are not affected by this issue.
Disabling the CRC Error Detection feature in your design compilation with the
Quartus II software will prevent this issue from occurring in ES devices.
This issue is fixed in production devices.
Automatic
Automatic with Manual Override
Switchover from inclk0 to inclk1, even though inclk0 is active (and vice-versa)
clkbad[0,1] status signals may glitch, even if the input clocks are active
March 2011 Altera Corporation
Stratix IV GX ES Family Issues