EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 36
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
- Current page: 36 of 332
- Download datasheet (4Mb)
1–36
Table 1–37. Output Timing Measurement Methodology for Output Pins (Part 3 of 3)
I/O Default Capacitive Loading
Stratix III Device Handbook, Volume 2
MINI-LVDS_E_1R
MINI-LVDS_E_3R
RSDS_E_1R
RSDS_E_3R
Notes to
(1) Hyper transport is not supported by Stratix III devices.
(2) LVPECL outputs are not supported by Stratix III devices.
(3) You can change the Quartus II timing conditions using the Advanced I/O Timing feature.
(4) V
(5) Terminated I/O standards require an additional 30 mV IR drop on V
(6) Terminated I/O standards require an additional 50 mV IR drop on V
I/O Standard
CC
is nominally 1.1 V less 50 mV (1.05 V).
Table
1–37:
Table 1–38
Table 1–38. Default Loading of Various I/O Standards for Stratix III Devices (Part 1 of 2)
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
3.0-V PCI
3.0-V PCI-X
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.2-V HSTL
Differential SSTL-2 CLASS I
Differential SSTL-2 CLASS II
Differential SSTL-18 CLASS I
120
120
—
—
R
S
100
100
100
100
R
lists the default capacitive loading of various I/O standards.
D
—
—
—
—
R
T
Loading and Termination
120
170
120
170
I/O Standard
R
P
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
2.325
2.325
2.325
2.325
CC
CCIO
V
(1.02 V).
CCIO
and V
CCPD
2.325
2.325
2.325
2.325
V
.
CCPD
1.02
1.02
1.02
1.02
V
CC
V
—
—
—
—
TT
© July 2010 Altera Corporation
C
Capacitive
L
(pF)
0
0
0
0
Load
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Measurement
V
1.1625
1.1625
1.1625
1.1625
Point
MEAS
I/O Timing
Unit
(v)
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
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