EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 213

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–103. EP3SE50 Column Pins Output Timing Parameters (Part 6 of 6)
Table 1–104. EP3SE50 Row Pins Output Timing Parameters (Part 1 of 5)
© July 2010 Altera Corporation
1.2-V
HSTL
CLASS I
1.2-V
HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
3.3-V
LVTTL
Standard
Standard
I/O
I/O
10mA
12mA
16mA
4mA
8mA
12mA
4mA
6mA
8mA
—
—
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Table 1–104
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
Industrial
Industrial
3.048
3.397
3.040
3.389
3.041
3.390
3.030
3.379
3.030
3.379
3.061
3.400
3.154
3.503
3.154
3.503
3.161
1.488
3.095
1.395
3.016
1.314
lists the EP3SE50 row pins output timing parameters for single-ended
Fast Model
Fast Model
Commercial
Commercial
3.058
3.371
3.050
3.363
3.051
3.364
3.040
3.353
3.040
3.353
3.061
3.374
3.164
3.477
3.164
3.477
3.395
1.692
3.324
1.587
3.235
1.493
4.317
4.777
4.308
4.768
4.315
4.775
4.302
4.762
4.302
4.762
4.318
4.778
4.363
4.823
4.363
4.823
4.722 5.117 5.622 5.486 5.755 5.247 5.754 5.618 5.832
2.101 2.185 2.381 2.400 2.349 2.304 2.505 2.523 2.344
4.612 5.005 5.508 5.372 5.611 5.134 5.638 5.502 5.683
1.971 2.047 2.237 2.256 2.205 2.163 2.356 2.374 2.195
4.506 4.905 5.412 5.276 5.483 5.035 5.539 5.403 5.551
1.852 1.924 2.109 2.128 2.077 2.036 2.224 2.242 2.063
1.1 V
V
1.1 V
V
C2
C2
CCL
CCL
=
=
4.683 5.208 5.088 5.302 4.683 5.208 5.088 5.302
5.212 5.710 5.565 5.864 5.212 5.710 5.565 5.864
4.668 5.191 5.071 5.290 4.668 5.191 5.071 5.290
5.203 5.701 5.556 5.855 5.203 5.701 5.556 5.855
4.674 5.187 5.067 5.293 4.674 5.187 5.067 5.293
5.212 5.710 5.565 5.864 5.212 5.710 5.565 5.864
4.661 5.164 5.044 5.287 4.661 5.164 5.044 5.287
5.198 5.696 5.551 5.850 5.198 5.696 5.551 5.850
4.661 5.165 5.045 5.279 4.661 5.165 5.045 5.279
5.198 5.697 5.552 5.851 5.198 5.697 5.552 5.851
4.685 5.243 5.123 5.316 4.685 5.243 5.123 5.316
5.213 5.710 5.565 5.864 5.213 5.710 5.565 5.864
4.710 5.218 5.098 5.347 4.710 5.218 5.098 5.347
5.247 5.735 5.590 5.889 5.247 5.735 5.590 5.889
4.710 5.218 5.098 5.347 4.710 5.218 5.098 5.347
5.247 5.735 5.590 5.889 5.247 5.735 5.590 5.889
1.1 V
1.1 V
V
V
C3
C3
CCL
CCL
=
=
1.1 V
V
1.1 V
V
C4
CCL
C4
CCL
=
=
1.1 V
V
1.1 V
V
CCL
CCL
=
=
C4L
C4L
Stratix III Device Handbook, Volume 2
0.9 V
V
0.9 V
V
CCL
CCL
=
=
1.1 V
V
1.1 V
V
CCL
I3
I3
CCL
=
=
1.1 V
V
1.1 V
I4
CCL
V
I4
CCL
=
=
1.1 V
V
1–213
CCL
1.1 V
V
CCL
=
I4L
=
I4L
0.9 V
V
CCL
0.9 V
V
CCL
=
=
Units
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns