EP1SGX40DF1020C6 Altera, EP1SGX40DF1020C6 Datasheet - Page 215

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EP1SGX40DF1020C6

Manufacturer Part Number
EP1SGX40DF1020C6
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX40DF1020C6

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Figure 6–2. Receiver Input Waveform Example with Values
Notes to
(1)
(2)
(3)
Figure 6–3. Transmitter Output Waveforms for Differential I/O Standards
Altera Corporation
June 2006
The values in this figure are for example only.
These values must meet the voltages specified in the section
If internal termination is used, the common mode is generated after the pins.
Figure
Single-Ended Waveform
Differential Waveform
Channel (p)
Channel (n)
Negative
Positive
6–2:
Ground
Single-Ended Waveform:
What is Applied
to the Pin (2)
Differential Waveform:
As Seen by the Buffer
or by Subtraction on an Oscilloscope
p - n = 0 V
V
CM
V
ID
V
ICM
Differential V
= 1.175 V (3)
V
ID
V
= 1 V
ID
ID
= 2 * V
(V ID (Differential) = 2 x V ID (single-ended))
V
ID
ID
= 1 V
(Single-Ended) = 2 V
“Operating Conditions” on page
Stratix GX Device Handbook, Volume 1
V
V
IH
ID
= 1.175 V + 0.5 V = 1.675 V
V
V
p − n = 0 V
IL
Positive Channel (p) = V
Negative Channel (n) = V
Ground
ID
= 1.175 V - 0.5 V = 0.675 V
= 1 V
DC & Switching Characteristics
6–1.
OH
OL
6–13

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