EP2S60F1020C4 Altera, EP2S60F1020C4 Datasheet - Page 70
EP2S60F1020C4
Manufacturer Part Number
EP2S60F1020C4
Description
IC STRATIX II FPGA 60K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F1020C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
718
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1131
EP2S60F1020C4ES
EP2S60F1020C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
EP2S60F1020C4
Manufacturer:
ALTERA
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Company:
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Company:
Part Number:
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Part Number:
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Manufacturer:
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Quantity:
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PLLs & Clock Networks
2–62
Stratix II Device Handbook, Volume 1
Figure 2–42. Global & Regional Clock Connections from Corner Clock Pins &
Fast PLL Outputs
Note to
(1)
The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input can be driven by an output from
another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated
global signal cannot drive the PLL.
Figure
2–42:
Note (1)
Altera Corporation
May 2007