EP2S60F1020C4 Altera, EP2S60F1020C4 Datasheet - Page 29
EP2S60F1020C4
Manufacturer Part Number
EP2S60F1020C4
Description
IC STRATIX II FPGA 60K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F1020C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
718
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1131
EP2S60F1020C4ES
EP2S60F1020C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F1020C4
Manufacturer:
ALTERA
Quantity:
1 238
Company:
Part Number:
EP2S60F1020C4
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S60F1020C4N
Manufacturer:
ALTERA
Quantity:
3
Part Number:
EP2S60F1020C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–15. Register Chain within an LAB
Note to
(1)
Altera Corporation
May 2007
The combinational or adder logic can be utilized to implement an unrelated, un-registered function.
Figure
2–15:
Combinational
Combinational
Logic
Logic
See the
information on register chain interconnect.
“MultiTrack Interconnect” on page 2–22
adder0
adder1
adder0
adder1
Note (1)
reg_chain_out
reg_chain_in
Stratix II Device Handbook, Volume 1
D
D
D
D
reg0
reg1
reg0
reg1
From Previous ALM
Within The LAB
To Next ALM
within the LAB
Q
Q
Q
Q
section for more
To general or
To general or
To general or
To general or
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
local routing
local routing
local routing
local routing
Stratix II Architecture
2–21