EP1S25F780C6 Altera, EP1S25F780C6 Datasheet - Page 229
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EP1S25F780C6
Manufacturer Part Number
EP1S25F780C6
Description
IC STRATIX FPGA 25K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F780C6
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
597
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1121
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
10
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
246
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1S25F780C6ES
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1S25F780C6N
Manufacturer:
ALTERA
Quantity:
1 045
Altera Corporation
January 2006
Table 4–98
clock to feed IOE registers in I/O banks around each device. These values
can be used for calculating the timing budget on the output (write) side
of a memory interface. These values already factor in the package skew.
Notes to
(1)
(2)
Note to
(1)
t
t
t
t
t
t
t
t
t
t
LR_HIO
TB_VIO
OVERALL
SB_HIO
SB_VIO
SS_HIO
SS_VIO
LR_HIO
TB_VIO
OVERALL
Table 4–97. Output Pin Timing Skew Definitions (Part 2 of 2)
Table 4–98. Output Skew for Stratix by Device Density
See
See
The skew numbers in
Symbol
Symbol
Table
Figure 4–5 on page
Figure 4–6 on page
Table
shows the I/O skews when using the same global or regional
4–98:
4–97:
EP1S10 to EP1S30
Across all HIO banks (1, 2, 5, 6); across four similar
type I/O banks
Across all VIO banks (3, 4, 7, 8); across four similar
type I/O banks
Output timing skew for all I/O pins on the device.
Table 4–98
4–57.
4–58.
160
180
150
190
430
90
90
account for worst case package skews.
Stratix Device Handbook, Volume 1
Skew (ps)
EP1S40
DC & Switching Characteristics
290
290
460
520
490
580
630
Definition
(1)
EP1S60 & EP1S80
500
500
600
630
600
670
880
4–59