EP1S25B672C7N Altera, EP1S25B672C7N Datasheet - Page 54
![IC STRATIX FPGA 25K LE 672-BGA](/photos/6/74/67408/ds-672bga05-2_0_sml.jpg)
EP1S25B672C7N
Manufacturer Part Number
EP1S25B672C7N
Description
IC STRATIX FPGA 25K LE 672-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25B672C7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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TriMatrix Memory
Figure 2–21. Left-Facing M-RAM to Interconnect Interface
Notes to
(1)
(2)
2–40
Stratix Device Handbook, Volume 1
Only R24 and C16 interconnects cross the M-RAM block boundaries.
The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6
orientation is clipped across the vertical axis for right-facing M-RAM blocks.
Figure
LABs in Row
M-RAM Boundary
Row Unit Interface
Allows LAB Rows to
Drive Address and
Control Signals to
M-RAM Block
2–21:
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
LAB Interface
Blocks
M512 RAM Block Columns
B1
A1
B2
A2
M-RAM Block
B3
A3
Port B
Port A
Notes
B4
A4
(1),
(2)
B5
A5
B6
A6
Column Interface Block
Allows LAB Columns to
Drive datain and dataout to
and from M-RAM Block
Altera Corporation
LABs in Column
M-RAM Boundary
Column Interface Block
Drives to and from
C4 and C8 Interconnects
July 2005
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