EP1S25B672C7N Altera, EP1S25B672C7N Datasheet - Page 212
![IC STRATIX FPGA 25K LE 672-BGA](/photos/6/74/67408/ds-672bga05-2_0_sml.jpg)
EP1S25B672C7N
Manufacturer Part Number
EP1S25B672C7N
Description
IC STRATIX FPGA 25K LE 672-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25B672C7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Timing Model
4–42
Stratix Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
INSU
INH
OUTCO
XZ
ZX
INSU
INH
OUTCO
XZ
ZX
INSUPLL
INHPLL
OUTCOPLL
XZPLL
ZXPLL
Table 4–67. EP1S25 External I/O Timing on Column Pins Using Fast Regional Clock Networks
Table 4–68. EP1S25 External I/O Timing on Column Pins Using Regional Clock Networks
Parameter
Parameter
2.412
0.000
2.196
2.136
2.136
1.535
0.000
2.739
2.679
2.679
0.934
0.000
1.316
1.256
1.256
-5 Speed Grade
-5 Speed Grade
Min
Min
4.475
4.349
4.349
5.396
5.270
5.270
2.733
2.607
2.607
Max
Max
Tables 4–67
and row pins for EP1S25 devices.
2.613
0.000
2.196
2.136
2.136
1.661
0.000
0.980
0.000
-6 Speed Grade
2.739
2.679
2.679
1.316
1.256
1.256
-6 Speed Grade
Min
Min
through
4.748
4.616
4.616
5.746
5.614
5.614
2.839
2.707
2.707
Max
Max
4–72
show the external timing parameters on column
2.968
0.000
2.196
2.136
2.136
1.877
0.000
2.739
2.679
2.679
1.092
0.000
1.316
1.256
1.256
-7 Speed Grade
-7 Speed Grade
Min
Min
5.118
4.994
4.994
6.262
6.138
6.138
2.921
2.797
2.797
Max
Max
3.468
0.000
2.196
2.136
2.136
-8 Speed Grade
2.125
0.000
2.739
2.679
2.679
1.231
0.000
1.316
1.256
1.256
-8 Speed Grade
Min
Min
Altera Corporation
5.603
5.488
5.488
6.946
6.831
6.831
3.110
2.995
2.995
Max
Max
January 2006
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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