EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 25

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Table 1–26. Single-Ended SSTL and HSTL I/O Standard Signal Specifications for Arria II GX Devices
Table 1–27. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria II GZ Devices (Part 1 of 2)
December 2010 Altera Corporation
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
I/O Standard
I/O Standard
Table 1–26
for Arria II GX devices.
Table 1–27
for Arria II GZ devices.
–0.15
–0.15
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Min
Min
-0.3
-0.3
-0.3
-0.3
—
V
V
IL(DC)
IL(DC)
(V)
(V)
V
V
V
V
V
0.125
V
0.125
V
V
V
V
V
V
V
V
V
0.125
V
0.125
V
0.15
0.15
Max
0.18
0.18
0.08
0.08
Max
lists the single-ended SSTL and HSTL I/O standard signal specifications
REF
REF
lists the single-ended SSTL and HSTL I/O standard signal specifications
0.1
REF
REF
REF
REF
REF
0.1
REF
0.1
REF
0.1
REF
0.1
REF
0.1
REF
0.1
REF
REF
REF
REF
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.125
0.125
0.125
0.125
0.15
0.15
0.18
0.18
0.08
0.08
Min
Min
REF
REF
REF
REF
REF
REF
REF
0.1
REF
REF
REF
0.1
REF
0.1
REF
0.1
REF
0.1
REF
0.1
REF
0.1
REF
REF
V
V
IH(DC)
IH(DC)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
(V)
(V)
Max
Max
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
0.15
CCIO
0.15
CCIO
CCIO
CCIO
CCIO
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
—
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V
V
V
V
V
V
V
V
V
V
V
V
V
V
REF
REF
IL(AC)
REF
REF
REF
REF
REF
REF
0.175
V
V
V
V
V
REF
REF
REF
REF
IL(AC)
Max
0.31
0.31
0.25
0.25
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
REF
REF
REF
REF
REF
Max
- 0.175
- 0.175
- 0.35
- 0.35
- 0.25
- 0.25
- 0.15
- 0.15
- 0.2
- 0.2
- 0.2
- 0.2
(V)
-
-
-
-
-
(V)
V
V
V
V
V
IH(AC)
V
V
V
V
V
V
0.175
0.31
0.31
0.25
0.25
REF
REF
REF
REF
Min
IH(AC)
REF
REF
REF
V
V
V
V
REF
REF
V
V
V
V
0.175
0.175
0.35
0.35
0.25
0.25
0.15
0.15
Min
REF
REF
REF
REF
REF
REF
REF
REF
+ 0.2
+ 0.2
+ 0.2
+ 0.2
(V)
+
+
+
+
+
(V)
+
+
+
+
+
+
+
+
V
0.475
0.2 ×
V
V
V
V
V
Max
0.57
0.76
0.28
0.25 ×
0.25 ×
OL
0.475
0.2 ×
0.2 ×
V
V
V
V
V
V
V
CCIO
Max
0.57
0.76
0.28
TT
TT
TT
OL
0.4
0.4
0.4
0.4
CCIO
CCIO
CCIO
CCIO
TT
TT
TT
(V)
-
-
-
(V)
-
-
-
V
V
0.475
V
V
V
V
0.8 ×
V
V
V
V
V
V
0.75 ×
0.75 ×
0.57
0.76
0.28
0.475
OH
Min
V
V
V
0.8 ×
0.8 ×
CCIO
V
V
V
V
0.57
0.76
0.28
OH
Min
TT
TT
TT
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
0.4
0.4
0.4
0.4
TT
TT
TT
CCIO
CCIO
CCIO
CCIO
(V)
+
+
+
(V)
+
+
+
-
-
-
-
-
-
(mA)
16.2
13.4
(mA)
16.4
13.4
8.1
6.7
8.1
6.7
I
I
16
16
16
14
8
OL
8
8
8
8
OL
–16.4
–13.4
-16.2
-13.4
(mA)
–8.1
–6.7
(mA)
–16
–16
–16
–14
-8.1
-6.7
I
1–17
–8
–8
–8
–8
I
-8
OH
OH