EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 94
EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number:
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ALTERA
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EP4CGX150CF23I7N
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5–32
Programmable Bandwidth
Phase Shift Implementation
Cyclone IV Device Handbook, Volume 1
Figure 5–20. VCO Switchover Operating Frequency
■
The PLL bandwidth is the measure of the PLL’s ability to track the input clock and its
associated jitter. PLLs of Cyclone IV devices provide advanced control of the PLL
bandwidth using the programmable characteristics of the PLL loop, including loop
filter and charge pump. The closed-loop gain 3-dB frequency in the PLL determines
the PLL bandwidth. The bandwidth is approximately the unity gain point for open
loop PLL response.
Phase shift is used to implement a robust solution for clock delays in Cyclone IV
devices. Phase shift is implemented with a combination of the VCO phase output and
the counter starting time. The VCO phase output and counter starting time are the
most accurate methods of inserting delays, because they are based only on counter
settings that are independent of process, voltage, and temperature.
You can phase shift the output clocks from the PLLs of Cyclone IV devices in one of
two ways:
■
■
Fine resolution phase shifts are implemented by allowing any of the output counters
(C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution.
Disable the system during switchover if the system is not tolerant to frequency
variations during the PLL resynchronization period. You can use the clkbad0
and clkbad1 status signals to turn off the PFD (pfdena = 0) so the VCO
maintains its last frequency. You can also use the switchover state machine to
switch over to the secondary clock. Upon enabling the PFD, output clock enable
signals (clkena) can disable clock outputs during the switchover and
resynchronization period. After the lock indication is stable, the system can
re-enable the output clock or clocks.
Fine resolution using VCO phase taps
Coarse resolution using counter starting time
F vco
Primary Clock Stops Running
Switchover Occurs
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
© December 2010 Altera Corporation
VCO Tracks Secondary Clock
Programmable Bandwidth
Frequency Overshoot
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