EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 64
EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX150CF23I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4CGX15BN11C8N PDF datasheet
- EP4CGX15BN11C8N PDF datasheet #2
- EP4CGX15BN11C8N PDF datasheet #3
- EP4CGX15BN11C8N PDF datasheet #4
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- Download datasheet (13Mb)
5–2
GCLK Network
Table 5–1. GCLK Network Connections for EP4CGX15, EP4CGX22, and EP4CGX30
Cyclone IV Device Handbook, Volume 1
CLK4/DIFFCLK_2n
CLK5/DIFFCLK_2p
CLK6/DIFFCLK_3n
CLK7/DIFFCLK_3p
CLK8/DIFFCLK_5n
CLK9/DIFFCLK_5p
CLK10/DIFFCLK_4n
/REFCLK1n
CLK11/DIFFCLK_4p
/REFCLK1p
CLK12/DIFFCLK_7p
/REFCLK0p
CLK13/DIFFCLK_7n
/REFCLK0n
CLK14/DIFFCLK_6p — — — — — — — — — — — — — — — —
CLK15/DIFFCLK_6n — — — — — — — — — — — — — — —
PLL_1_C0
PLL_1_C1
PLL_1_C2
PLL_1_C3
PLL_1_C4
PLL_2_C0
PLL_2_C1
PLL_2_C2
PLL_2_C3
PLL_2_C4
PLL_3_C0
PLL_3_C1
PLL_3_C2
PLL_3_C3
GCLK Network Clock
Sources
GCLKs drive throughout the entire device, feeding all device quadrants. All resources
in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks,
and M9K memory blocks) can use GCLKs as clock sources. Use these clock network
resources for control signals, such as clock enables and clears fed by an external pin.
Internal logic can also drive GCLKs for internally generated GCLKs and
asynchronous clears, clock enables, or other control signals with high fan-out.
Table
clock sources to the GCLK networks.
v
v
v
v
— — — — —
— — — — — —
— — — — — —
— — — — —
— — — — — — — — — —
— — — — — — — — — — —
— — — — — — — — — — —
— — — — — — — — — —
— — — — — — — — — — — — — — —
— — — — — — — — — — — — — — — —
—
—
— —
—
—
— —
— — — — —
— — — — — —
— — — — —
— — — — — —
0
5–1,
v
v
v
v
— —
—
— —
—
1
Table 5–2 on page
v
v
v
v
— —
—
— —
—
2
v
v
v
v
— — — — — — — — — — — —
—
— — — — — — —
—
3
v
v
v
v
— — — — — — — — — — —
— — — — — — — — — — — —
— — — — — —
— — — — — — —
4
v
v
v
v
— — — — — — — — — — —
— — — — — — — — — — — —
— — — — — —
— — — — — — —
5
v v
v
v
v
—
— —
— —
—
5–4, and
6
v
v
—
— —
—
7
—
— — — — — — — — — — — —
v v
v
v
— — — — — — —
v
8
GCLK Networks
Table 5–3 on page 5–7
v
v
— — — — — — — — — — —
— — — — — —
— — — — — — —
9
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
10 11 12 13 14 15 16 17 18 19
— — — — — — — — — —
— — — — — — — — — —
v
v
v
v
— — — — — —
v v
v
v
v
—
— —
— —
—
(Note
v
v
v
—
— —
—
1),
—
— — — — — — —
v v
v
v
— — — — — — —
v
—
© December 2010 Altera Corporation
(2)
list the connectivity of the
v
v
v
— — — — — —
— — — — — —
— — — — — —
(Part 1 of 2)
— — — — —
— — — — —
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v
v
v
— — — — —
— — — — —
v
v
v v
v
v
v
v
v
—
— —
— —
—
— —
—
v
—
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v
—
v
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v
—
Clock Networks
v v
v
v
v
v
v
—
— —
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v
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