EP3CLS70F484I7N Altera, EP3CLS70F484I7N Datasheet - Page 37

• Manufacturer Part Number: EP3CLS70F484I7N
• Description: IC FPGA CYCIII LS 70K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3CLS70F484I7N

• Number Of Logic Elements/cells: 70208
• Number Of Labs/clbs: 4388
• Total Ram Bits: 3068928
• Number Of I /o: 278
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III LS
• Number Of Logic Blocks/elements: 70208
• # I/os (max): 278
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 70208
• Ram Bits: 3068928
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone III Device Data Sheet
I/O Timing
I/O Timing
Glossary
Table 1–39. Glossary (Part 1 of 5)
© January 2010 Altera Corporation
Letter
D
G
H
A
B
C
E
F
I
f
GCLK
GCLK PLL
HSIODR
Input Waveforms
for the SSTL
Differential I/O
Standard
HS CLK
f
Term
—
—
—
—
—
You can use the following methods to determine the I/O timing:
■
■
The Excel-based I/O Timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
The Excel-based I/O Timing spreadsheet is downloadable from
Literature
Table 1–39
the Excel-based I/O Timing.
the Quartus II timing analyzer.
V
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.
Input pin directly to Global Clock network.
Input pin to Global Clock network through PLL.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
SWING
website.
lists the glossary for this chapter.
Definitions
—
—
—
—
—
Cyclone III Device Handbook, Volume 2
Cyclone III Devices
V
V
V
REF
IH
IL
1–27