EP3CLS70F484I7N Altera, EP3CLS70F484I7N Datasheet - Page 28
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EP3CLS70F484I7N
Manufacturer Part Number
EP3CLS70F484I7N
Description
IC FPGA CYCIII LS 70K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3CLS70F484I7N.pdf
(274 pages)
Specifications of EP3CLS70F484I7N
Number Of Logic Elements/cells
70208
Number Of Labs/clbs
4388
Total Ram Bits
3068928
Number Of I /o
278
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone III LS
Number Of Logic Blocks/elements
70208
# I/os (max)
278
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
70208
Ram Bits
3068928
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1–18
Periphery Performance
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications
Cyclone III Device Handbook, Volume 2
f
(input clock
frequency)
HSC LK
Symbol
Table 1–25
Table 1–25. Cyclone III Devices JTAG Timing Parameters
High-Speed I/O Specifications
Table 1–26
For definitions of high-speed timing specifications, refer to
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes to
(1) For more information about JTAG waveforms, refer to
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS
JC P
JC H
JC L
JP SU_TDI
JP SU_TM S
JP H
JP CO
JP ZX
JP XZ
JS SU
JS H
JS CO
JS ZX
JS XZ
Symbol
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Modes
Table
×10
×8
×7
×4
×2
×1
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for TDI
JTAG port setup time for TMS
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
lists the JTAG timing parameters and values for Cyclone III devices.
through
1–25:
Table 1–31
Min
10
10
10
10
10
10
Typ
C6
—
—
—
—
—
—
list the high-speed I/O timing for Cyclone III devices.
(2)
Parameter
(2)
Max
180
180
180
180
180
360
(2)
(2)
Min
10
10
10
10
10
10
“JTAG Waveform”
(Note
(2)
(2)
C7, I7
Typ
—
—
—
—
—
—
1),
(Note 1)
155.5
155.5
155.5
155.5
155.5
Max
(2)
311
Chapter 1: Cyclone III Device Data Sheet
in
(Part 1 of 2)
“Glossary” on page
© January 2010 Altera Corporation
“Glossary” on page
Min
10
10
10
10
10
10
C8, A7
Typ
Switching Characteristics
Min
—
—
—
—
—
—
40
20
20
10
—
—
—
10
—
—
—
1
3
5
1–27.
155.5
155.5
155.5
155.5
155.5
Max
311
Max
—
—
—
—
—
—
15
15
15
—
—
25
25
25
1–27.
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns