EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 192

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

8–26
Figure 8–9. Word-Wide Multi-Device AP Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
(5) The AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,
(6) Connect the repeater buffers between the Cyclone IV E master device and slave devices for DATA[15..0] and DCLK. All I/O inputs must
Cyclone IV Device Handbook, Volume 1
devices in FPP mode. To connect MSEL[3..0] for the master device in AP mode and the slave devices in FPP mode, refer to
page
you can optionally use the normal I/O pin to monitor the WAIT signal from the Numonyx P30 or P33 flash.
maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
“Configuration and JTAG Pin I/O Requirements” on page
Figure
8–9. Connect the MSEL pins directly to V
Numonyx P30/P33 Flash
8–9:
1
DQ[15:0]
In a multi-device AP configuration, the board trace length between the parallel flash
and the master device must follow the recommendations listed in
A[24:1]
RST#
ADV#
WAIT
WE#
OE#
CLK
CE#
CCIO
CCIO
GND
10 k
supply voltage of the I/O bank in which the nCE pin resides.
V CCIO (1)
supply of the bank in which the pin resides.
Buffers (6)
nCE
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O (5)
DATA[15..0]
PADD[23..0]
CCA
10 k
Master Device
Cyclone IV E
V CCIO (1)
or GND.
MSEL[3..0]
10 k
V CCIO (1)
8–5.
nCEO
DQ[15..8]
10 k
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
V CCIO (2)
DQ[7..0]
(4)
Cyclone IV E Slave Device
Cyclone IV E Slave Device
nCE
DATA[7..0]
DCLK
nCE
DATA[7..0]
DCLK
MSEL[3..0]
MSEL[3..0]
nCEO
10 k
nCEO
V CCIO (1)
10 k
V CCIO (2)
DQ[15..8]
DQ[7..0]
(4)
(4)
Cyclone IV E Slave Device
Cyclone IV E Slave Device
nCE
DATA[7..0]
DCLK
nCE
DATA[7..0]
DCLK
© December 2010 Altera Corporation
MSEL[3..0]
MSEL[3..0]
nCEO
nCEO
Table
(4)
N.C. (3)
(4)
N.C. (3)
8–9.
Table 8–5 on
Configuration