EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 183

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
Equation 8–2.
Equation 8–3.
Altera recommends putting a buffer before the DATA and DCLK output from the
master device to avoid signal strength and signal integrity issues. The buffer must not
significantly change the DATA-to-DCLK relationships or delay them with respect to
other AS signals (ASDI and nCS). Also, the buffer must only drive the slave devices to
ensure that the timing between the master device and the serial configuration device
is unaffected.
This configuration method supports both compressed and uncompressed .sof.
Therefore, if the configuration bitstream size exceeds the capacity of a serial
configuration device, you can enable the compression feature in the .sof or you can
select a larger serial configuration device.
Guidelines for Connecting a Serial Configuration Device to Cyclone IV Devices for
an AS Interface
For single- and multi-device AS configurations, the board trace length and loading
between the supported serial configuration device and Cyclone IV device must follow
the recommendations listed in
Table 8–6. Maximum Trace Length and Loading for AS Configuration
Estimating AS Configuration Time
AS configuration time is dominated by the time it takes to transfer data from the serial
configuration device to the Cyclone IV device. This serial interface is clocked by the
Cyclone IV device DCLK output (generated from a 40-MHz internal oscillator for
Cyclone IV E devices, a 20- or 40-MHz internal oscillator, or an external CLKUSR of up
to 40 MHz for Cyclone IV GX devices).
configuration time calculations.
Enabling compression reduces the amount of configuration data that is sent to the
Cyclone IV device, which also reduces configuration time. On average, compression
reduces configuration time by 50%.
Device AS Pins
Cyclone IV
DATA[0]
DCLK
nCSO
ASDO
RBF Size
Cyclone IV Device to a Serial Configuration



Maximum Board Trace Length from a
maximum DCLK period
------------------------------------------------------ -
Cyclone IV E
10
10
10
10
1 bit
9,600,000 bits
Device (Inches)
Table
8–6.


Equation 8–2

Cyclone IV GX
=


50 ns
------------ -
estimated maximum configuration time
1 bit
6
6
6
6


=
480 ms
and
Equation 8–3
Cyclone IV Device Handbook, Volume 1
Maximum Board Load (pF)
15
30
30
30
show the
8–17