EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 98

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–36
Figure 5–22. PLL Reconfiguration Scan Chain
Cyclone IV Device Handbook, Volume 1
scanclkena
configupdate
scandataout
scandone
scandata
inclk
scanclk
1
The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, not all counters update simultaneously.
To reconfigure the PLL counters, perform the following steps:
1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
3. After all 144 bits have been scanned into the scan chain, the scanclkena signal is
4. The configupdate signal is asserted for one scanclk cycle to update the PLL
5. The scandone signal goes high indicating that the PLL is being reconfigured. A
6. Reset the PLL using the areset signal if you make any changes to the M, N,
7. You can repeat steps
from M counter
from N counter
/C4
the first bit of scandata (D0).
scanclk.
de-asserted to prevent inadvertent shifting of bits in the scan chain.
counters with the contents of the scan chain.
falling edge indicates that the PLL counters have been updated with new settings.
post-scale output C counters, or the I
/C3
1
PFD
through
/C2
5
to reconfigure the PLL any number of times.
LF/K/CP
CP
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
/C1
, R, C settings.
/C0
VCO
© December 2010 Altera Corporation
/M
F
PLL Reconfiguration
VCO
/N