EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 338

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–58
Cyclone IV Device Handbook, Volume 2
1
1
If you have the auto negotiation state machine in the FPGA fabric, the rate match
FIFO is also capable of deleting or inserting the first two bytes of the /C2/ ordered set
(/K28.5/D2.2/Dx.y/Dx.y/) to prevent the rate match FIFO from overflowing or
under running during the auto negotiation phase.
The status flags rx_rmfifodatadeleted and rx_rmfifodatainserted to
indicate rate match FIFO deletion and insertion events, respectively, are forwarded to
the FPGA fabric. These two flags are asserted for two clock cycles for each deleted and
inserted /I2/ ordered set.
Figure 1–58
be deleted. Because the rate match FIFO can only delete /I2/ ordered sets, it deletes
two /I2/ ordered sets (four symbols deleted).
Figure 1–58. Example of Rate Match FIFO Deletion in GIGE Mode
Figure 1–59
symbol must be inserted. Because the rate match FIFO can only insert /I2/ ordered
sets, it inserts one /I2/ ordered set (two symbols inserted).
Figure 1–59. Example of Rate Match FIFO Insertion in GIGE Mode
The rate match FIFO does not insert or delete code groups automatically to overcome
FIFO empty or full conditions. In this case, the rate match FIFO asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least two recovered clock cycles
to indicate rate match FIFO full and empty conditions, respectively. You must then
assert the rx_digitalreset signal to reset the receiver PCS blocks.
rx_rmfifodatainserted
rx_rmfifodatadeleted
shows an example of rate match FIFO deletion where three symbols must
shows an example of rate match FIFO insertion in the case where one
dataout
dataout
datain
datain
Dx.y
Dx.y
Dx.y
Dx.y
K28.5
K28.5
K28.5
K28.5
First /I2/ Skip
Ordered Set
Ordered Set
First /I2/
/I2/ Skip Symbol Deleted
D16.2
D16.2
D16.2
D16.2
Second /I2/ Skip
K28.5
K28.5
K28.5
Dx.y
Ordered Set
Ordered Set
Second /I2/
Chapter 1: Cyclone IV Transceivers Architecture
D16.2
D16.2
D16.2
© December 2010 Altera Corporation
K28.5
K28.5
Third /I2/ Skip
Ordered Set
Transceiver Functional Modes
D16.2
D16.2
Dx.y
Dx.y