EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 364

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–84
Table 1–28. PIPE Interface Ports in ALTGX Megafunction for Cyclone IV GX
Table 1–29. Multipurpose PLL, General Purpose PLL and Miscellaneous Ports in ALTGX Megafunction for
Cyclone IV GX (Part 1 of 2)
Cyclone IV Device Handbook, Volume 2
rx_elecidle
infersel
Note to
(1) For equivalent signals defined in PIPE 2.00 specification, refer to
PLL
Block
Port Name
Table
pll_inclk
pll_locked
pll_areset
coreclkout
1–28:
Port Name
Output
Input/
Input
N/A
Clock Domain
Output
Input
Output
Input
Output
Input/
Clock signal
Asynchronous signal
Asynchronous signal
Clock signal
Clock Domain
Table 1–15 on page
Controls the electrical idle inference mechanism as specified in
on page 1–53
Input reference clock for the PLL (multipurpose PLL or general
purpose PLL) used by the transceiver instance. When configured
with the transmitter and receiver channel configuration in
Deterministic Latency mode, multiple pll_inclk ports are
available as follows.
Configured with PLL PFD feedback—x is the number of channels
selected:
■
■
Configured without PLL PFD feedback:
■
■
PLL (used by the transceiver instance) lock indicator.
PLL (used by the transceiver instance) reset.
■
■
FPGA fabric-transceiver interface clock in bonded modes.
1–50.
(Note 1)
pll_inclk[x-1..0] are input reference clocks for each
transmitter in the transceiver instance
pll_inclk[x+1..x] are input reference clocks for
receivers in the transceiver instance
pll_inclk[0] is input reference clock for transmitters in
the transceiver instance
pll_inclk[1] is input reference clock for receivers in the
transceiver instance
When asserted, the PLL is kept in reset state.
When deasserted, the PLL is active and locks to the input
reference clock.
Chapter 1: Cyclone IV Transceivers Architecture
(Part 2 of 2)
Description
© December 2010 Altera Corporation
Transceiver Top-Level Port Lists
Description
Table 1–17