EP3C5E144I7 Altera, EP3C5E144I7 Datasheet - Page 41

• Manufacturer Part Number: EP3C5E144I7
• Description: IC CYCLONE III FPGA 5K 144 EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5E144I7

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Design and Compilation
PLL Considerations
© November 2008 Altera Corporation
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For more information on the support and implementation, refer to the On-Chip
Termination Support section in the
the Cyclone III Device Handbook.
Dedicated Differential Output Buffer with Programmable Pre-Emphasis
Cyclone III devices provide dedicated differential output buffers on left and right I/O
banks. These buffers are capable of transmitting LVDS signals at up to 840 Mbps
without requiring external resistors. Similarly, you can transmit RSDS, mini-LVDS,
and PPDS with dedicated transmitter buffers with no external resistors required at
different speeds. Only a differential termination resistor is required on the receiver.
The top and bottom I/O banks can transmit differential I/O standards, but require an
additional resistor network on the transmitter. You can implement the serializer and
deserializer (SERDES) for LVDS using the altlvds megafunction in the Quartus II
software. SERDES is implemented in core logic as Cyclone III devices do not have a
dedicated SERDES circuit.
For more information on the support and implementation, refer to the
Differential Interfaces in Cyclone III Devices
Handbook.
Programmable pre-emphasis is supported on dedicated differential output buffers to
maximize the data eye opening at the far-end receiver. High speed interfaces that use
long traces typically suffer high frequency signal attenuation in the transmission
media due to skin effect and dielectric loss. Programmable pre-emphasis reduces the
attenuation, by boosting high frequency component at each transition in the data
stream. To enable this in the Quartus II software, set Programmable Pre-emphasis
assignment for the pin to On in the Assignment Editor.
Post PLL Design
After designing the PLL, consider the following topics before designing the board.
Choosing the PLL
For Cyclone III devices, there are four identical PLLs (except EP3C5 and EP3C10,
which have only two identical PLLs). You can choose to use a specific PLL or let the
Quartus II software choose the best PLL to use. For the first option, you must choose
the PLL where you have available suitable dedicated input and output clock pins. The
PLL input clock must be either dedicated input clock pins or another PLL output. The
PLL input clock cannot be driven from internal logic. The PLL output clock should be
connected to its dedicated clock output pin for optimum routing (only applies to c0),
user I/O, or global clock (GCLK).
To obtain the locations of the PLLs and their corresponding pins, refer to the
corresponding device pin-outs and
chapter in volume 1 of the Cyclone III Device Handbook.
Pin Assignment
The following are the recommended pin assignments in the Quartus II software for
the PLL input and output ports.
Cyclone III Device I/O Features
Clock Networks and PLLs in Cyclone III Devices
chapter in volume 1 of the Cyclone III Device
chapter in volume 1 of
High-Speed
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