EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 350

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–70
Cyclone IV Device Handbook, Volume 2
Registered Mode Phase Compensation FIFO
In Deterministic Latency mode, the RX phase compensation FIFO is set to registered
mode while the TX phase compensation FIFO supports optional registered mode.
When set into registered mode, the phase compensation FIFO acts as a register and
eliminates the latency uncertainty through the FIFOs.
Receive Bit-Slip Indication
The number of bits slipped in the word aligner for synchronization in manual
alignment mode is provided with the rx_bitslipboundaryselectout[4..0]
signal. For example, if one bit is slipped in word aligner to achieve synchronization,
the output on rx_bitslipboundaryselectout[4..0] signal shows a value of 1
(5'00001). The information from this signal helps in latency calculation through the
receiver as the number of bits slipped in the word aligner varies at each
synchronization.
Transmit Bit-Slip Control
The transmitter datapath supports bit-slip control to delay the serial data
transmission by a number of specified bits in PCS with
tx_bitslipboundaryselect[4..0] port. With 8- or 10-bit channel width, the
transmitter supports zero to nine bits of data slip. This feature helps to maintain a
fixed round trip latency by compensating latency variation from word aligner when
providing the appropriate values on tx_bitslipboundaryselect[4..0] port
based on values on rx_bitslipboundaryselectout[4..0] signal.
PLL PFD feedback
In Deterministic Latency mode, when transmitter input reference clock frequency is
the same as the low-speed clock, the PLL that clocks the transceiver supports PFD
feedback. When enabled, the PLL compensates for delay uncertainty in the low-speed
clock (tx_clkout in ×1 configuration or coreclkout in ×4 configuration) path
relative to input reference and the transmitter datapath latency is fixed relative to the
transmitter input reference clock.
Chapter 1: Cyclone IV Transceivers Architecture
© December 2010 Altera Corporation
Transceiver Functional Modes