EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 366
EP4CE6E22C8N
Manufacturer Part Number
EP4CE6E22C8N
Description
IC CYCLONE IV FPGA 6K 144EQFP
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE6E22C8N
Number Of Logic Elements/cells
6272
Number Of Labs/clbs
392
Total Ram Bits
270000
Number Of I /o
91
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-EQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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EP4CE6E22C8N
Manufacturer:
AD
Quantity:
1 200
Company:
Part Number:
EP4CE6E22C8N
Manufacturer:
ALTERA
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1–86
Document Revision History
Table 1–30. Document Revision History
Cyclone IV Device Handbook, Volume 2
December 2010
November 2010
July 2010
Date
Revision
Table 1–30
3.1
3.2
3.0
lists the revision history for this chapter.
■
■
■
■
■
Updated Introductory information.
■
■
Updated for the Quartus II software version 10.1 release.
Updated
Table
Updated
“Clock Data
Receiver PCS
“Channel
Modes”
Added
Updated
Figure
Updated information for the Quartus II software version 10.0 release.
Reset control, power down, and dynamic reconfiguration information moved to
new Cyclone IV Reset Control and Power Down and Cyclone IV Dynamic
Reconfiguration chapters.
1–26,
1–70,
Figure
sections.
Table
“8B/10B
Figure
Deskewing”,
Table
Recovery”,
Figure
1–9,
Feature”,
1–1,
1–53,
1–27,
Encoder”,
Figure
Table
1–71,
Figure
“Lane
“Input Reference
“Miscellaneous Transmitter PCS
Table
1–5,
1–10,
Figure
“Transmitter Output
1–55,
Synchronization”,
1–28, and
Table
Figure
Changes Made
1–72,
Figure
1–11,
1–19,
Figure
Table
Clocking”,
Chapter 1: Cyclone IV Transceivers Architecture
1–59,
Table
Figure
1–73, and
1–29.
“Serial
Figure
1–14,
Buffer”,
© December 2010 Altera Corporation
“PCI Express (PIPE)
1–20, and
Loopback”, and
Table
1–60,
Features”,
Figure
“Receiver Input
1–24,
Document Revision History
Figure
Figure
1–74.
Table
“Miscellaneous
1–69,
1–43.
“Self Test
Mode”,
1–25,
Buffer”,
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