EP1S20F672C7 Altera, EP1S20F672C7 Datasheet - Page 266

• Manufacturer Part Number: EP1S20F672C7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672C7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1113

PLL Specifications
4–96
Stratix Device Handbook, Volume 1
t
t
t
f
t
t
f
% spread
t
f
f
f
f
t
t
t
f
f
SCANCLK
DLOCK
LOCK
VCO
LSKEW
SKEW
SS
ARESET
IN
INPFD
INDUTY
EINDUTY
INJITTER
EINJITTER
FCOMP
OUT
OUT_EXT
Table 4–128. Enhanced PLL Specifications for -6 Speed Grades
Table 4–129. Enhanced PLL Specifications for -7 Speed Grade (Part 1 of 2)
Symbol
Symbol
scanclk frequency
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
(11)
Time required to lock from end of
device configuration
PLL internal VCO operating range
Clock skew between two external
clock outputs driven by the same
counter
Clock skew between two external
clock outputs driven by the different
counters with the same settings
Spread spectrum modulation
frequency
Percentage spread for spread
spectrum frequency
Minimum pulse width on
signal
Input clock frequency
Input frequency to PFD
Input clock duty cycle
External feedback clock input duty
cycle
Input clock period jitter
External feedback clock period jitter
External feedback clock
compensation time
Output frequency for internal global
or regional clock
Output frequency for external clock
(3)
Parameter
Parameter
(4)
(10)
(5)
(11)
areset
(7)
(1),
Min
Min
0.3
0.3
300
0.4
40
40
(9)
10
30
10
3
3
(2)
±50
±75
Typ
0.5
Typ
(Part 2 of 2)
±200
±200
800
Max
100
400
150
Max
565
420
420
434
0.6
22
60
60
6
(8)
(3)
(3)
Altera Corporation
January 2006
MHz
MHz
Unit
MHz
MHz
MHz
MHz
kHz
Unit
μs
μs
ps
ps
ns
%
ps
ps
ns
%
%