XC5VLX30T-1FFG665C Xilinx Inc, XC5VLX30T-1FFG665C Datasheet - Page 360
XC5VLX30T-1FFG665C
Manufacturer Part Number
XC5VLX30T-1FFG665C
Description
IC FPGA VIRTEX-5 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665C
Total Ram Bits
1327104
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
No. Of Logic Blocks
4800
No. Of Gates
30000
No. Of Macrocells
4800
No. Of Speed Grades
1
No. Of I/o's
360
Clock Management
PLL
Dc
1045
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1560
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Chapter 8: Advanced SelectIO Logic Resources
360
ISERDES_NODELAY Clocking Methods
NUM_CE Attribute
SERDES_MODE Attribute
Networking Interface Type
X-Ref Target - Figure 8-5
The NUM_CE attribute defines the number of clock enables (CE1 and CE2) used. The
possible values are 1 and 2 (default = 2).
The SERDES_MODE attribute defines whether the ISERDES_NODELAY module is a
master or slave when using width expansion. The possible values are MASTER and
SLAVE. The default value is MASTER. See
The phase relationship of CLK and CLKDIV is important in the serial-to-parallel
conversion process. CLK and CLKDIV are (ideally) phase-aligned within a tolerance.
There are several clocking arrangements within the FPGA to help the design meet the
phase relationship requirements of CLK and CLKDIV. The only valid clocking
arrangements for the ISERDES_NODELAY block using the networking interface type are:
•
•
•
Figure 8-5: Internal Connections of ISERDES_NODELAY When in Memory Mode
CLK driven by BUFIO, CLKDIV driven by BUFR
CLK driven by DCM, CLKDIV driven by the CLKDV output of the same DCM
CLK driven by PLL, CLKDIV driven by CLKOUT[0:5] of same PLL
CLKDIV
OCLK
CLK
D
ICE
ICE
FF0
FF1
www.xilinx.com
ICE
ICE
ISERDES Width
FF2
FF3
FF4
FF5
Expansion.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
FF6
FF7
FF8
FF9
ug190_8_05_100307
Q1
Q2
Q3
Q4
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