XC5VLX30T-1FFG665C Xilinx Inc, XC5VLX30T-1FFG665C Datasheet - Page 124
XC5VLX30T-1FFG665C
Manufacturer Part Number
XC5VLX30T-1FFG665C
Description
IC FPGA VIRTEX-5 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665C
Total Ram Bits
1327104
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
No. Of Logic Blocks
4800
No. Of Gates
30000
No. Of Macrocells
4800
No. Of Speed Grades
1
No. Of I/o's
360
Clock Management
PLL
Dc
1045
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1560
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Chapter 4: Block RAM
124
Figure 4-9
(RAMB36).
X-Ref Target - Figure 4-9
Table 4-5: Virtex-5 FPGA Block RAM, FIFO, Simple Dual Port, and ECC Primitives
Notes:
1. All eight primitives are described in the software Libraries guide as well as the language templates.
RAMB36
RAMB36SDP
FIFO36
FIFO36_72
RAMB18
RAMB18SDP
FIFO18
FIFO18_36
Primitive
illustrates all the I/O ports of the 36 Kb true dual-port block RAM primitive
Table 4-5
Supports port widths of x1, x2, x4, x9, x18, x36
Simple dual port (port width x72) and 64-bit ECC primitive (see
Figure
Supports port widths of x4, x9, x18, x36
FIFO (port width x72), optional ECC support
Supports port widths of x1, x2, x4, x9, x18
Simple dual port (port width x36)
Supports port widths of x4, x9, x18
FIFO (port width x36)
Figure 4-9: Block RAM Port Signals (RAMB36)
lists these primitives.
CASCADEOUTREGA
CASCADEOUTLATA
32
16
32
16
CASCADEINREGA
www.xilinx.com
4
4
4
4
4-29)
CASCADEINLATA
DIA
DIPA
ADDRA
WEA
ENA
REGCEA
SSRA
DIB
DIPB
ADDRB
WEB
ENB
REGCEB
SSRB
CLKA
CLKB
CASCADEINLATB
CASCADEINREGB
Description
CASCADEOUTLATB
CASCADEOUTREGB
DOPA
DOPB
DOA
DOB
ug0190_4_10_100906
32
32
4
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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