XC5VLX30T-1FFG665C Xilinx Inc, XC5VLX30T-1FFG665C Datasheet - Page 163
XC5VLX30T-1FFG665C
Manufacturer Part Number
XC5VLX30T-1FFG665C
Description
IC FPGA VIRTEX-5 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665C
Total Ram Bits
1327104
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
No. Of Logic Blocks
4800
No. Of Gates
30000
No. Of Macrocells
4800
No. Of Speed Grades
1
No. Of I/o's
360
Clock Management
PLL
Dc
1045
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1560
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Table 4-22: FIFO ECC Port Names and Descriptions
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Notes:
1. Hamming code implemented in the FIFO ECC logic detects one of three conditions: no detectable error, single-bit error detected and
DI[63:0]
DIP[7:0]
WREN
RDEN
RST
WRCLK
RDCLK
DO[63:0]
DOP[7:0]
SBITERR
DBITERR
ECCPARITY[7:0]
FULL
ALMOSTFULL
EMPTY
ALMOSTEMPTY
RDCOUNT
WRCOUNT
WRERR
RDERR
corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and DBITERR
indicate these three conditions.
Port Name
(1)
(1)
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Table 4-22
Data input bus.
Data input parity bus. Not used when standard mode is used.
Write enable. When WREN = 1, data will be written into memory. When WREN = 0,
write is disabled
Read enable. When RDEN = 1, data will be read from memory. When RDEN = 0, read
is disabled.
Asynchronous reset of FIFO counter and flags. Reset must be asserted for three clock
cycles. Reset does not affect DO or ECC signals.
Clock for write operations.
Clock for read operations.
Data output bus.
Data output parity bus.
Single-bit error status.
Double-bit error status.
ECC encoder output bus.
FIFO FULL flag.
FIFO ALMOSTFULL flag.
FIFO EMPTY flag.
The FIFO data read pointer.
The FIFO data write pointer.
When the FIFO is full, any additional write operation generates an error flag.
When the FIFO is empty, any additional read operation generates an error flag.
FIFO ALMOSTEMPTY flag.
lists and describes the FIFO ECC I/O port names.
www.xilinx.com
Signal Description
Built-in Error Correction
163
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