EP1AGX90EF1152C6N Altera, EP1AGX90EF1152C6N Datasheet - Page 153

• Manufacturer Part Number: EP1AGX90EF1152C6N
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152C6N

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2379

Chapter 4: DC and Switching Characteristics
I/O Timing Model
Table 4–45. Timing Measurement Methodology for Input Pins
Clock Network Skew Adders
Table 4–46. Clock Network Specifications
Default Capacitive Loading of Different I/O Standards
© December 2009 Altera Corporation
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
LVDS
LVPECL
Notes to
(1) Input buffer sees no load at buffer input.
(2) Input measuring point at buffer input is 0.5 V
(3) Output measuring point is 0.5 V
(4) Input edge rate is 1 V/ns.
(5) Less than 50-mV ripple on V
(6) V
Clock skew adder
EP1AGX20/35
Clock skew adder
EP1AGX50/60
Clock skew adder
EP1AGX90
Note to
(1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
CCPD
Table
Table
= 2.97 V, less than 50-mV ripple on V
Name
(1)
I/O Standard
4–46:
4–45:
(1)
(1)
The Quartus II software models skew within dedicated clock networks such as global
and regional clocks. Therefore, the intra-clock network skew adder is not specified.
Table 4–46
registers in the Arria GX device.
See
Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 1 of 2)
LVTTL
LVCMOS
2.5 V
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Table 4–47
CCIO
CC
and V
at internal node.
specifies the intra clock skew between any two clock networks driving any
CCPD
I/O Standard
, V
for default capacitive loading of different I/O standards.
CCIO
Description
CCIO
CCINT
V
and V
.
1.660
1.375
1.375
1.660
1.660
2.325
3.135
CCIO
= 1.15 V with less than 30-mV ripple.
CCPD
(V)
, V
Measurement Conditions
CCINT
= 1.15 V.
V
0.830
0.688
0.688
0.830
0.830
REF
(Note
—
—
(V)
Min
Capacitive Load
—
—
—
—
—
—
1), (2), (3),
Edge Rate (ns)
0
0
0
Typ
—
—
—
—
—
—
1.660
1.375
1.375
1.660
1.660
0.100
0.100
(4)
(Part 2 of 2)
± 100
± 100
± 110
± 50
Max
± 50
± 55
Arria GX Device Handbook, Volume 1
Measurement Point
Units
Units
VMEAS (V)
ps
ps
ps
ps
ps
ps
pF
pF
pF
0.6875
0.6875
1.1625
1.5675
0.83
0.83
0.83
4–31