EP1AGX90EF1152C6N Altera, EP1AGX90EF1152C6N Datasheet - Page 113

• Manufacturer Part Number: EP1AGX90EF1152C6N
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152C6N

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2379

Introduction
IEEE Std. 1149.1 JTAG Boundary-Scan Support
© December 2009 Altera Corporation
AGX51003-2.0
1
All Arria
with the IEEE Std. 1149.1. You can perform JTAG boundary-scan testing either before
or after, but not during configuration. Arria GX devices can also use the JTAG port for
configuration with the Quartus
or jam byte-code files (.jbc).
This chapter contains the following sections:
■
■
■
■
Arria GX devices support I/O element (IOE) standard setting reconfiguration through
the JTAG BST chain. The JTAG chain can update the I/O standard for all input and
output pins any time before or during user-mode through the CONFIG_IO
instruction. You can use this capability for JTAG testing before configuration when
some of the Arria GX pins drive or receive from other devices on the board using
voltage-referenced standards. Because the Arria GX device may not be configured
before JTAG testing, the I/O pins may not be configured for appropriate electrical
standards for chip-to-chip communication. Programming these I/O standards via
JTAG allows you to fully test the I/O connections to other devices.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK,
and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor,
while the TDI, TMS, and TRST pins have weak internal pull-up resistors. The JTAG
input pins are powered by the 3.3-V V
V
Arria GX devices also use the JTAG port to monitor the logic operation of the device
with the SignalTap
instructions shown in
Arria GX, Cyclone
devices must be within the first 17 devices in a JTAG chain. All of these devices have
the same JTAG controller. If any of the Stratix, Arria GX, Cyclone, and Cyclone II
devices are in the 18th or further position, they will fail configuration. This does not
affect the functionality of the SignalTap
CCIO
“IEEE Std. 1149.1 JTAG Boundary-Scan Support”
“SignalTap II Embedded Logic Analyzer” on page 3–3
“Configuration” on page 3–3
“Automated Single Event Upset (SEU) Detection” on page 3–8
power supply in I/O bank 4.
®
GX devices provide JTAG boundary-scan test (BST) circuitry that complies
®
®
II, Cyclone, Stratix
II embedded logic analyzer. Arria GX devices support the JTAG
Table
3–1.
®
II software or hardware using either jam files (.jam)
CCPD
®
®
, Stratix II, Stratix GX , and Stratix II GX
3. Configuration and Testing
II embedded logic analyzer.
pins. The TDO output pin is powered by the
Arria GX Device Handbook, Volume 1