EP2S30F484C5 Altera, EP2S30F484C5 Datasheet - Page 87
![IC STRATIX II FPGA 30K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S30F484C5
Manufacturer Part Number
EP2S30F484C5
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C5
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1107
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C5
Manufacturer:
ALTERA
Quantity:
648
Company:
Part Number:
EP2S30F484C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F484C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–53. Input Timing Diagram in DDR Mode
Altera Corporation
May 2007
Input To
Logic Array
Data at
input pin
CLK
B0
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from ALMs on rising clock edges.
These output registers are multiplexed by the clock to drive the output
pin at a ×2 rate. One output register clocks the first bit out on the clock
high time, while the other output register clocks the second bit out on the
clock low time.
Figure 2–55
A0
B1
A0
B0
A1
shows the DDR output timing diagram.
Figure 2–54
B2
A1
B1
A2
B3
A2
B2
shows the IOE configured for DDR output.
A3
B4
A3
B3
Stratix II Device Handbook, Volume 1
Stratix II Architecture
2–79