EPF81500AQC240-2 Altera, EPF81500AQC240-2 Datasheet - Page 2

• Manufacturer Part Number: EPF81500AQC240-2
• Description: IC FLEX 8000A FPGA 16K 240-PQFP
• Manufacturer: Altera
• Series: FLEX 8000r

Specifications of EPF81500AQC240-2

• Number Of Logic Elements/cells: 1296
• Number Of Labs/clbs: 162
• Number Of I /o: 181
• Number Of Gates: 16000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: FLEX 8000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1296
• # Registers: 1500
• # I/os (max): 181
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 1296
• Ram Bits: 8
• Device System Gates: 16000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2249

FLEX 8000 Programmable Logic Device Family Data Sheet
...and More
Features
Note:
(1)
General
Description
2
JTAG BST circuitry
EPF8282A
EPF8282AV
EPF8452A
EPF8636A
EPF8820A
EPF81188A
EPF81500A
Table 2. FLEX 8000 Package Options & I/O Pin Count
Device
FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad
flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages.
PLCC
84-
Pin
68
68
68
TQFP
100-
Pin
78
78
68
Altera’s Flexible Logic Element MatriX (FLEX
benefits of both erasable programmable logic devices (EPLDs) and field-
programmable gate arrays (FPGAs). The FLEX 8000 device family is ideal
for a variety of applications because it combines the fine-grained
architecture and high register count characteristics of FPGAs with the
high speed and predictable interconnect delays of EPLDs. Logic is
implemented in LEs that include compact 4-input look-up tables (LUTs)
and programmable registers. High performance is provided by a fast,
continuous network of routing resources.
Yes
TQFP
144-
112
Pin
Peripheral register for fast setup and clock-to-output delay
Fabricated on an advanced SRAM process
Available in a variety of packages with 84 to 304 pins (see
Software design support and automatic place-and-route provided by
the Altera
PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM
RISC System/6000 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and Veribest
PQFP
160-
120
118
120
Pin
®
No
MAX+PLUS
160-
PGA
120
Pin
192-
PGA
136
152
Pin
Note (1)
Yes
®
II development system for Windows-based
PQFP
208-
136
152
148
Pin
225-
BGA
Yes
152
Pin
®
232-
PGA
184
) family combines the
Pin
PQFP
No
240-
184
181
Pin
Altera Corporation
280-
PGA
208
Pin
Table
Yes
RQFP
304-
208
Pin
2)