EP2C35F484C8N Altera, EP2C35F484C8N Datasheet - Page 149

• Manufacturer Part Number: EP2C35F484C8N
• Description: IC CYCLONE II FPGA 35K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C35F484C8N

• Number Of Logic Elements/cells: 33216
• Number Of Labs/clbs: 2076
• Total Ram Bits: 483840
• Number Of I /o: 322
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 33216
• # I/os (max): 322
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33216
• Ram Bits: 483840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2076
• Family Type: Cyclone II
• No. Of I/o's: 322
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1366; EP2C35F484C8N

Figure 5–5. RSDS Transmitter Clock to Data Relationship
Altera Corporation
February 2008
f
(input
clock
frequency)
H S C L K
Table 5–49. Mini-LVDS Transmitter Timing Specification (Part 1 of 2)
Symbol
Conditions
rx_data[11..0]
tx_data[11..0]
At transmitter
×10
Channel-to-Channel
At receiver
×8
×7
×4
×2
×1
Skew (1.68 ns)
Table 5–49
devices at 311 Mbps. Cyclone II devices cannot receive mini-LVDS data
because the devices are intended for applications where they will be
driving display drivers. A maximum mini-LVDS data rate of 311 Mbps is
supported for Cyclone II devices using DDIO registers. Cyclone II
devices support mini-LVDS only in the commercial temperature range.
Min
10
10
10
10
10
10
–6 Speed Grade
Clock (5.88 ns)
Transmitter
Typ
—
—
—
—
—
—
t
SU
Skew
Total
(2 ns)
shows the mini-LVDS transmitter timing budget for Cyclone II
155.5
155.5
155.5
155.5
155.5
Max
311
Transmitter
Valid
Valid
Data
Data
Min
10
10
10
10
10
10
t
–7 Speed Grade
H
(2 ns)
DC Characteristics and Timing Specifications
Typ
—
—
—
—
—
—
Transmitter
Cyclone II Device Handbook, Volume 1
Valid
Valid
Data
Data
155.5
155.5
155.5
155.5
155.5
Max
311
Min
10
10
10
10
10
10
–8 Speed Grade
Typ
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
Max
311
MHz
MHz
MHz
MHz
MHz
MHz
Unit
5–59