EP2C35F484C8N Altera, EP2C35F484C8N Datasheet - Page 53
![IC CYCLONE II FPGA 35K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2C35F484C8N
Manufacturer Part Number
EP2C35F484C8N
Description
IC CYCLONE II FPGA 35K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F484C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
322
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
33216
# I/os (max)
322
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
33216
Ram Bits
483840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
322
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1366
EP2C35F484C8N
EP2C35F484C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F484C8N
Manufacturer:
ALTERA
Quantity:
319
Part Number:
EP2C35F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–23. Signal Path Through the I/O Block
Altera Corporation
February 2007
From Logic
To Logic
Array
Array
Row or Column
io_cce_out
io_clk[5..0]
io_dataout
io_datain0
io_datain1
io_cce_in
io_caclr
io_csclr
io_cclk
io_coe
The pin’s datain signals can drive the logic array. The logic array drives
the control and data signals, providing a flexible routing resource. The
row or column IOE clocks, io_clk[5..0], provide a dedicated routing
resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions (see
“Global Clock Network & Phase-Locked Loops” on page
Figure 2–23
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out.
selection.
Data and
Selection
Control
Signal
illustrates the signal paths through the I/O block.
oe
ce_in
ce_out
aclr/preset
sclr/preset
clk_in
clk_out
dataout
Figure 2–24
To Other
IOEs
Cyclone II Device Handbook, Volume 1
illustrates the control signal
IOE
Cyclone II Architecture
2–16).
2–41