EP2C20F256C6N Altera, EP2C20F256C6N Datasheet - Page 64

IC CYCLONE II FPGA 20K 256-FBGA

EP2C20F256C6N

Manufacturer Part Number
EP2C20F256C6N
Description
IC CYCLONE II FPGA 20K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C20F256C6N

Number Of Logic Elements/cells
18752
Number Of Labs/clbs
1172
Total Ram Bits
239616
Number Of I /o
152
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
For Use With
P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1660

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I/O Structure & Features
2–52
Cyclone II Device Handbook, Volume 1
3.3-V LVTTL and LVCMOS
(1)
2.5-V LVTTL and LVCMOS
1.8-V LVTTL and LVCMOS
1.5-V LVCMOS
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
HSTL-18 class I
HSTL-18 class II
HSTL-15 class I
HSTL-15 class II
PCI and PCI-X
Differential SSTL-2 class I or
class II
Differential SSTL-18 class I
or class II
Table 2–17. Cyclone II Supported I/O Standards & Constraints (Part 1 of 2)
I/O Standard
(1) (3)
Advanced I/O Standard Support
Table 2–17
which I/O pins support them.
Single ended
Single ended
Single ended
Single ended
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Single ended
Pseudo
differential
Pseudo
differential
Type
(4)
(4)
shows the I/O standards supported by Cyclone II devices and
3.3 V/
3.3 V/
1.8 V/
1.8 V/
Input Output
2.5 V
2.5 V
1.5 V
1.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
3.3 V
2.5 V
1.8 V
V
(5)
(5)
CCIO
Level
3.3 V
2.5 V
1.8 V
1.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
3.3 V
2.5 V
1.8 V
(5)
(5)
CLK,
DQS
Top & Bottom
v
v
v
v
v
v
v
v
v
v
v
v
v
v
(6)
(6)
I/O Pins
User I/O
Pins
v
v
v
v
v
v
v
v
v
v
v
v
CLK,
DQS
v
v
v
v
v
v
v
(2)
v
(2)
v
(2)
v
v
(6)
v
(6)
PLL_OUT
Side I/O Pins
v
Altera Corporation
v
v
v
v
v
v
v
v
v
v
v
(2)
(2)
(2)
(7)
February 2007
User I/O
Pins
v
v
v
v
v
v
v
v
v
v
(2)
(2)
(2)

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