EP2C5F256I8 Altera, EP2C5F256I8 Datasheet - Page 160

IC CYCLONE II FPGA 5K 256-FBGA

EP2C5F256I8

Manufacturer Part Number
EP2C5F256I8
Description
IC CYCLONE II FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5F256I8

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
158
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2132

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Duty Cycle Distortion
5–70
Cyclone II Device Handbook, Volume 1
Here is an example for calculating the DCD as a percentage for an SDR
output on a row I/O on a –6 device:
If the SDR output I/O standard is SSTL-2 Class II, the maximum DCD is
65 ps (refer to
period T is:
To calculate the DCD as a percentage:
Notes to
(1)
(2)
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential HSTL-18 Class I
Differential HSTL-15 Class I
LVDS
Simple RSDS
Mini LVDS
PCI
PCI-X
LVCMOS
LVTTL
Table 5–55. Maximum DCD for Single Data Outputs (SDR) on Row I/O
Pins
Table 5–56. Maximum DCD for SDR Output on Column I/O
(Part 1 of 2)
Column I/O Output Standard
T = 1/ f = 1 / 167 MHz = 6 ns = 6000 ps
(T/2 – DCD) / T = (6000 ps/2 – 65 ps) / 6000 ps = 48.91% (for low
boundary)
(T/2 + DCD) / T = (6000 ps/2 + 65 ps) / 6000ps = 51.08% (for high
boundary
Row I/O Output Standard
The DCD specification is characterized using the maximum drive strength
available for each I/O standard.
Numbers are applicable for commercial, industrial, and automotive devices.
Notes
Table
(1),
5–55:
Table
(2)
5–55). If the clock frequency is 167 MHz, the clock
(Part 2 of 2)
145
195
195
C6
60
65
90
85
60
60
60
195
210
C6
165
155
145
255
255
C7
60
60
60
90
75
285
305
C7
Altera Corporation
165
155
205
255
255
Notes
C8
90
75
60
60
60
285
305
C8
February 2008
(1),
Unit
(2)
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps

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