EP2C5T144C7 Altera, EP2C5T144C7 Datasheet - Page 75
![IC CYCLONE II FPGA 5K 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP2C5T144C7
Manufacturer Part Number
EP2C5T144C7
Description
IC CYCLONE II FPGA 5K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C5T144C7
Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
89
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1449
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2C5T144C7
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP2C5T144C7N
Manufacturer:
ALTERA
Quantity:
364
Part Number:
EP2C5T144C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
IEEE Std. 1149.1
(JTAG) Boundary
Scan Support
Altera Corporation
February 2007
CII51003-2.2
f
All Cyclone
the IEEE Std. 1149.1. JTAG boundary-scan testing can be performed
either before or after, but not during configuration. Cyclone II devices can
also use the JTAG port for configuration with the Quartus
hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
Cyclone II devices support IOE I/O standard reconfiguration through the
JTAG BST chain. The JTAG chain can update the I/O standard for all
input and output pins any time before or during user mode through the
CONFIG_IO instruction. You can use this capability for JTAG testing
before configuration when some of the Cyclone II pins drive or receive
from other devices on the board using voltage-referenced standards.
Since the Cyclone II device might not be configured before JTAG testing,
the I/O pins may not be configured for appropriate electrical standards
for chip-to-chip communication. Programming the I/O standards via
JTAG allows you to fully test I/O connections to other devices.
For information on I/O reconfiguration, refer to the MorphIO: An I/O
Reconfiguration Solution for Altera Devices White Paper.
A device operating in JTAG mode uses four required pins: TDI, TDO, TMS,
and TCK. The TCK pin has an internal weak pull-down resister, while the
TDI and TMS pins have weak internal pull-up resistors. The TDO output
pin and all JTAG input pin voltage is determined by the V
where it resides. The bank V
1.8-, 2.5-, or 3.3-V compatible.
1
Stratix
within the first 8 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II, Stratix,
Cyclone II or Cyclone devices are in the 9th of further position,
they fail configuration. This does not affect Signal Tap II.
®
II devices provide JTAG BST circuitry that complies with
®
II, Stratix, Cyclone II and Cyclone devices must be
3. Configuration & Testing
CCIO
selects whether the JTAG inputs are 1.5-,
CCIO
®
II software or
of the bank
3–1