EP2C5T144C7 Altera, EP2C5T144C7 Datasheet - Page 47
![IC CYCLONE II FPGA 5K 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP2C5T144C7
Manufacturer Part Number
EP2C5T144C7
Description
IC CYCLONE II FPGA 5K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C5T144C7
Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
89
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1449
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2C5T144C7
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP2C5T144C7N
Manufacturer:
ALTERA
Quantity:
364
Part Number:
EP2C5T144C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2007
There is only one signa and one signb signal for each dedicated
multiplier. Therefore, all of the data A inputs feeding the same dedicated
multiplier must have the same sign representation. Similarly, all of the
data B inputs feeding the same dedicated multiplier must have the same
sign representation. The signa and signb signals can be changed
dynamically to modify the sign representation of the input operands at
run time. The multiplier offers full precision regardless of the sign
representation and can be registered using dedicated registers located at
the input register stage.
Multiplier Modes
Table 2–12
multipliers can operate in.
18-bit Multiplier
9-bit Multiplier
Table 2–12. Embedded Multiplier Modes
Multiplier Mode
summarizes the different modes that the embedded
An embedded multiplier can be configured to support a
single 18 × 18 multiplier for operand widths up to 18 bits.
All 18-bit multiplier inputs and results can be registered
independently. The multiplier operands can accept
signed integers, unsigned integers, or a combination of
both.
An embedded multiplier can be configured to support
two 9 × 9 independent multipliers for operand widths up
to 9-bits. Both 9-bit multiplier inputs and results can be
registered independently. The multiplier operands can
accept signed integers, unsigned integers or a
combination of both.
There is only one signa signal to control the sign
representation of both data A inputs and one signb
signal to control the sign representation of both data B
inputs of the 9-bit multipliers within the same dedicated
multiplier.
Cyclone II Device Handbook, Volume 1
Description
Cyclone II Architecture
2–35