EP2C5T144C7 Altera, EP2C5T144C7 Datasheet - Page 41
![IC CYCLONE II FPGA 5K 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP2C5T144C7
Manufacturer Part Number
EP2C5T144C7
Description
IC CYCLONE II FPGA 5K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C5T144C7
Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
89
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1449
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2C5T144C7
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP2C5T144C7N
Manufacturer:
ALTERA
Quantity:
364
Part Number:
EP2C5T144C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2007
Note to
(1)
Maximum performance
Total RAM bits per M4K block (including parity bits)
Configurations supported
Parity bits
Byte enable
Packed mode
Address clock enable
Memory initialization file (.mif)
Power-up condition
Register clears
Same-port read-during-write
Mixed-port read-during-write
Table 2–6. M4K Memory Features
Maximum performance information is preliminary until device characterization.
Table
2–6:
Feature
(1)
Table 2–6
summarizes the features supported by the M4K memory.
250 MHz
4,608
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32 (not available in true dual-port mode)
128 × 36 (not available in true dual-port mode)
One parity bit for each byte. The parity bit, along with
internal user logic, can implement parity checking for
error detection to ensure data integrity.
a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits. The
byte enables allow the input data to be masked so the
device can write to specific bytes. The unwritten bytes
retain the previous written value.
Two single-port memory blocks can be packed into a
single M4K block if each of the two independent block
sizes are equal to or less than half of the M4K block
size, and each of the single-port memory blocks is
configured in single-clock mode.
used to hold the previous address value for as long as
the signal is enabled. This feature is useful in handling
misses in cache applications.
When configured as RAM or ROM, you can use an
initialization file to pre-load the memory contents.
Output registers only
New data available at positive clock edge
4K × 1
M4K blocks support byte writes when the write port has
M4K blocks support address clock enable, which is
Outputs cleared
Old data available at positive clock edge
Cyclone II Device Handbook, Volume 1
Description
Cyclone II Architecture
2–29